Yoshiki Kawajiri

11 papers Journal 11

Year	Rank	Type	Title / Venue / Authors
1999	J	`jnl`	A 29-mm IEEE J. Solid State Circuits Yoshikazu Miyawaki, Osamu Ishizaki, Yoshihiko Okihara, Tsutomu Inaba, Fumihiko Nitta, Masaaki Mihara, Takashi Hayasaka, Kazuo Kobayashi, Tadashi Omae, Hiroshi Kimura, Satoshi Shimizu, Hiromi Makimoto, Yoshiki Kawajiri, Masashi Wada, Hirofumi Sonoyama, Jun Etoh
1994	J	`jnl`	A charge recycle refresh for Gb-scale DRAM's in file applications. IEEE J. Solid State Circuits Takayulu Kawahara, Yoshiki Kawajiri, Masashi Horiguchi, Takesada Akiba, Goro Kitsukawa, Tokuo Kure, Masakazu Aoki
1993	J	`jnl`	256-Mb DRAM circuit technologies for file applications. IEEE J. Solid State Circuits Goro Kitsukawa, Masashi Horiguchi, Yoshiki Kawajiri, Takayuki Kawahara, Takesada Akiba, Yasushi Kawase, Toshikazu Tachibana, Takeshi Sakai, Masakazu Aoki, Syoji Shukuri, Kazuhiko Sagara, Ryo Nagai, Yuzuru Ohji, Nono Hasegawa, Natsuki Yokoyama, Teruaki Kisu, Hisaomi Yamashita, Tokuo Kure, Takashi Nishida
1993	J	`jnl`	A high-speed, small-area, threshold-voltage-mismatch compensation sense amplifier for gigabit-scale DRAM arrays. IEEE J. Solid State Circuits Takayuki Kawahara, Takeshi Sakata, Kiyoo Itoh, Yoshiki Kawajiri, Takesada Akiba, Goro Kitsukawa, Masakazu Aoki
1993	J	`jnl`	Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs). IEEE J. Solid State Circuits Takayuki Kawahara, Masashi Horiguchi, Yoshiki Kawajiri, Goro Kitsukawa, Tokuo Kure, Masakazu Aoki
1992	J	`jnl`	Deep-submicrometer BiCMOS circuit technology for sub-10-ns ECL 4-Mb DRAM's. IEEE J. Solid State Circuits Takayuki Kawahara, Yoshiki Kawajiri, Goro Kitsukawa, Kazuhiko Sagara, Yoshifumi Kawamoto, Takesada Akiba, Shisei Kato, Yasushi Kawase, Kiyoo Itoh
1991	J	`jnl`	A circuit technology for sub-10-ns ECL 4-Mb BiCMOS DRAM's. IEEE J. Solid State Circuits Takayuki Kawahara, Yoshiki Kawajiri, Goro Kitsukawa, Yoshinobu Nakagome, Kazuhiko Sagara, Yoshifumi Kawamoto, Takesada Akiba, Shisei Kato, Yasushi Kawase, Kiyoo Itoh
1990	J	`jnl`	A 23-ns 1-Mb BiCMOS DRAM. IEEE J. Solid State Circuits Goro Kitsukawa, Kazumasa Yanagisawa, Yutaka Kobayashi, Yoshitaka Kinoshita, Tatsuyuki Ohta, Tetsu Udagawa, Hitoshi Miwa, Hiroyuki Miyazawa, Yoshiki Kawajiri, Yoshiaki Ouchi, Hiromi Tsukada, Tetsuro Matsumoto, Kiyoo Itoh
1989	J	`jnl`	A 1-Mbit BiCMOS DRAM using temperature-compensation circuit techniques. IEEE J. Solid State Circuits Goro Kitsukawa, Kiyoo Itoh, Ryoichi Hori, Yoshiki Kawajiri, Takao Watanabe, Takayuki Kawahara, Tetsuro Matsumoto, Yutaka Kobayashi
1989	J	`jnl`	Comparison of CMOS and BiCMOS 1-Mbit DRAM performance. IEEE J. Solid State Circuits Takao Watanabe, Goro Kitsukawa, Yoshiki Kawajiri, Kiyoo Itoh, Ryoichi Hori, Yoshiaki Ouchi, Takayuki Kawahara, Tetsuro Matsumoto
1989	J	`jnl`	Substrate current reduction techniques for BiCMOS DRAM. IEEE J. Solid State Circuits Takayuki Kawahara, Goro Kitsukawa, Hisayuki Higuchi, Yoshiki Kawajiri, Takao Watanabe, Kiyoo Itoh, Ryoichi Hori, Yutaka Kobayashi, Tetsuro Matsumoto