Yoshihito Amemiya

67 papers B 7C 3Journal 41Unranked 16

Year	Rank	Type	Title / Venue / Authors
2011	—	`conf`	A 0.6-4.5 GHz inductorless CMOS low noise amplifier with gyrator-C network. ICECS Akira Kondou, Masayuki Ikebe, Junichi Motohisa, Yoshihito Amemiya, Eiichi Sano
2011	J	`jnl`	Neuro-morphic Circuit Architectures Employing Temporal Noises and Device Fluctuations to Improve Signal-to-noise Ratio in a Single-electron Pulse-density Modulator. Int. J. Unconv. Comput. Andrew Kilinga Kikombo, Tetsuya Asai, Yoshihito Amemiya
2010	J	`jnl`	A 1-muhboxW 600- hboxppm/ IEEE Trans. Circuits Syst. II Express Briefs Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2010	J	`jnl`	A CMOS Phase-Shift oscillator Based on the conduction of Heat. J. Circuits Syst. Comput. Takaaki Hirai, Tetsuya Asai, Yoshihito Amemiya
2010	J	`jnl`	A behavioral model of unipolar resistive RAMs and its application to HSPICE integration. IEICE Electron. Express Nobuo Akou, Tetsuya Asai, Takeshi Yanagida, Tomoji Kawai, Yoshihito Amemiya
2010	J	`jnl`	An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs. IEICE Trans. Electron. Yusuke Tsugita, Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2010	—	`conf`	Array-Enhanced Stochastic Resonance in a Network of Noisy Neuromorphic Circuits. ICONIP (1) Gessyca Maria Tovar, Tetsuya Asai, Yoshihito Amemiya
2010	J	`jnl`	High-Resistance Resistor Consisting of a Subthreshold CMOS Differential Pair. IEICE Trans. Electron. Shin'ichi Asai, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya
2009	—	`conf`	A 30-MHz, 90-ppm/°C fully-integrated clock reference generator with frequency-locked loop. ESSCIRC Ken Ueno, Tetsuya Asai, Yoshihito Amemiya
2009	J	`jnl`	A 300 nW, 15 ppm°C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs. IEEE J. Solid State Circuits Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2009	—	`conf`	A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs. ASP-DAC Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2009	B	`conf`	A pulse-density modulation circuit exhibiting noise shaping with single-electron neurons. IJCNN Andrew Kilinga Kikombo, Tetsuya Asai, Takahide Oya, Alexandre Schmid, Yusuf Leblebici, Yoshihito Amemiya
2009	—	`conf`	Exploiting Temporal Noises and Device Fluctuations in Enhancing Fidelity of Pulse-Density Modulator Consisting of Single-Electron Neural Circuits. ICONIP (2) Andrew Kilinga Kikombo, Tetsuya Asai, Yoshihito Amemiya
2009	J	`jnl`	Low-Voltage Process-Compensated VCO with On-Chip Process Monitoring and Body-Biasing Circuit Techniques. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2009	C	`conf`	Low-power Clock Reference Circuit for Intermittent Operation of Subthreshold LSIs. ISCAS Ken Ueno, Tetsuya Asai, Yoshihito Amemiya
2009	—	`conf`	Offset cancellation with subthreshold-operated feedback circuit for fully differential amplifiers. ICECS Tomoki Iida, Tetsuya Asai, Eiichi Sano, Yoshihito Amemiya
2009	C	`conf`	On-chip PVT Compensation Techniques for Low-voltage CMOS Digital LSIs. ISCAS Yusuke Tsugita, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya, Tetsuya Hirose
2009	—	`conf`	Pulse-Density Modulation with an Ensemble of Single-Electron Circuits Employing Neuronal Heterogeneity to Achieve High Temporal Resolution. NanoNet Andrew Kilinga Kikombo, Tetsuya Asai, Yoshihito Amemiya
2009	J	`jnl`	Stochastic Resonance in an Array of Locally-Coupled McCulloch-Pitts Neurons with Population Heterogeneity. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Akira Utagawa, Tohru Sahashi, Tetsuya Asai, Yoshihito Amemiya
2009	J	`jnl`	Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Taichi Ogawa, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2008	—	`conf`	A 0.3μW, 7 ppm/°C CMOS Voltage reference circuit for on-chip process monitoring in analog circuits. ESSCIRC Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2008	J	`jnl`	Noise-Induced Synchronization among Sub-RF CMOS Analog Oscillators for Skew-Free Clock Distribution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
2008	—	`conf`	Noise-Tolerant Analog Circuits for Sensory Segmentation Based on Symmetric STDP Learning. ICONIP (2) Gessyca Maria Tovar, Tetsuya Asai, Yoshihito Amemiya
2008	J	`jnl`	On Digital LSI Circuits Exploiting Collision-Based Fusion Gates. Int. J. Unconv. Comput. Kazuhito Yamada, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
2008	J	`jnl`	Temperature-compensated CMOS current reference circuit for ultralow-power subthreshold LSIs. IEICE Electron. Express Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2007	J	`jnl`	A CMOS Reaction-diffusion Device Using Minority-Carrier Diffusion in Semiconductors. Int. J. Bifurc. Chaos Motoyoshi Takahashi, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
2007	J	`jnl`	A Single-Electron Reaction-Diffusion Device for Computation of a Voronoi Diagram. Int. J. Unconv. Comput. Takahide Oya, Tetsuya Asai, Yoshihito Amemiya
2007	J	`jnl`	A subthreshold CMOS circuit for a piecewise linear neuromorphic oscillator with current-mode low-pass filters. Neurocomputing Kazuki Nakada, Tetsuya Asai, Tetsuya Hirose, Hatsuo Hayashi, Yoshihito Amemiya
2007	J	`jnl`	An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
2007	—	`conf`	Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning. ICONIP (2) Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
2007	J	`jnl`	CMOS Smart Sensor for Monitoring the Quality of Perishables. IEEE J. Solid State Circuits Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2007	J	`jnl`	Discrete Dynamical Systems Consisting of Single-electron Circuits. Int. J. Bifurc. Chaos Andrew Kilinga Kikombo, Takahide Oya, Tetsuya Asai, Yoshihito Amemiya
2007	C	`conf`	Floating millivolt reference for PTAT current generation in Subthreshold MOS LSIs. ISCAS Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2007	B	`conf`	Neuromorphic CMOS Circuits implementing a Novel Neural Segmentation Model based on Symmetric STDP Learning. IJCNN Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
2006	J	`jnl`	A CMOS Watchdog Sensor for Certifying the Quality of Various Perishables with a Wider Activation Energy. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2006	J	`jnl`	A subthreshold Analog MOS Circuit for Lotka-volterra Chaotic oscillator. Int. J. Bifurc. Chaos Tetsuya Asai, Taishi Kamiya, Tetsuya Hirose, Yoshihito Amemiya
2006	J	`jnl`	Design methodologies for compact logic circuits based on collision-based computing. IEICE Electron. Express Kazuhito Yamada, Ikuko N. Motoike, Tetsuya Asai, Yoshihito Amemiya
2006	J	`jnl`	Power-supply circuits for ultralow-power subthreshold MOS-LSIs. IEICE Electron. Express Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
2006	J	`jnl`	Single-Electron Logic Systems Based on a Graphical Representation of Digital Functions. IEICE Trans. Electron. Yoshihito Amemiya
2005	J	`jnl`	A quadrilateral-object composer for binary images with reaction-diffusion cellular automata. Parallel Algorithms Appl. Tetsuya Asai, Masayuki Ikebe, Tetsuya Hirose, Yoshihito Amemiya
2005	J	`jnl`	Analog CMOS implementation of a CNN-based locomotion controller with floating-gate devices. IEEE Trans. Circuits Syst. I Regul. Pap. Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya
2005	—	`conf`	Analog CMOS implementation of a neuromorphic oscillator with current-mode low-pass filters. ISCAS (3) Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya
2005	J	`jnl`	Analog Reaction-Diffusion Chip Imitating Belousov-Zhabotinsky Reaction with Hardware Oregonator Model. Int. J. Unconv. Comput. Tetsuya Asai, Yusuke Kanazawa, Tetsuya Hirose, Yoshihito Amemiya
2005	B	`conf`	Analog current-mode CMOS implementation of central pattern generator for robot locomotion. IJCNN Kazuki Nakada, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
2005	B	`conf`	Noise performance of single-electron depressing synapses for neuronal synchrony detection. IJCNN Takahide Oya, Tetsuya Asai, Ryo Kagaya, Yoshihito Amemiya
2005	J	`jnl`	On the fault tolerance of a clustered single-electron neural network for differential enhancement. IEICE Electron. Express Takahide Oya, Alexandre Schmid, Tetsuya Asai, Yusuf Leblebici, Yoshihito Amemiya
2005	J	`jnl`	Reaction-Diffusion Systems Consisting of Single-Electron Oscillators. Int. J. Unconv. Comput. Takahide Oya, Tetsuya Asai, Takashi Fukui, Yoshihito Amemiya
2005	—	`conf`	Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture. ISCAS (3) Takahide Oya, Tetsuya Asai, Yoshihito Amemiya, Alexandre Schmid, Yusuf Leblebici
2005	J	`jnl`	Ultralow-Power Current Reference Circuit with Low Temperature Dependence. IEICE Trans. Electron. Tetsuya Hirose, Toshimasa Matsuoka, Kenji Taniguchi, Tetsuya Asai, Yoshihito Amemiya
2004	J	`jnl`	A MOS circuit for bursting neural oscillators with excitable oregonators. IEICE Electron. Express Yusuke Kanazawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
2004	B	`conf`	A MOS circuit for depressing synapse and its application to contrast-invariant pattern classification and synchrony detection. IJCNN Tetsuya Asai, Yusuke Kanazawa, Tetsuya Hirose, Yoshihito Amemiya
2004	J	`jnl`	A Novel CMOS Circuit for Depressing Synapse and its Application to Contrast-Invariant Pattern Classification and Synchrony Detection. Int. J. Robotics Autom. Yusuke Kanazawa, Tetsuya Asai, Masayuki Ikebe, Yoshihito Amemiya
2004	—	`conf`	An analog CMOS chip implementing a CNN-based locomotion controller for quadruped walking robots. ISCAS (3) Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya
2004	J	`jnl`	Biologically-Inspired Locomotion Controller for a Quadruped Walking Robot: Analog IC Implementation of a CPG-Based Controller. J. Robotics Mechatronics Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya
2004	J	`jnl`	Design of an Artificial Central Pattern Generator with Feedback Controller. Intell. Autom. Soft Comput. Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya
2004	J	`jnl`	Reaction-diffusion chip implementing excitable lattices with multiple-valued cellular automata. IEICE Electron. Express Hiroshi Matsubara, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
2003	J	`jnl`	A subthreshold MOS neuron circuit based on the Volterra system. IEEE Trans. Neural Networks Tetsuya Asai, Yusuke Kanazawa, Yoshihito Amemiya
2003	J	`jnl`	An analog CMOS central pattern generator for interlimb coordination in quadruped locomotion. IEEE Trans. Neural Networks Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya
2003	B	`conf`	An analog neural oscillator circuit for locomotion controller in quadruped walking robot. IJCNN Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya
2003	J	`jnl`	Basic Circuit Design of a Neural Processor: Analog CMOS Implementation of Spiking Neurons and Dynamic Synapses. J. Robotics Mechatronics Yusuke Kanazawa, Tetsuya Asai, Yoshihito Amemiya
2003	—	`conf`	Biomorphic Analog Devices based on Reaction-Diffusion Systems. ISMVL Tetsuya Asai, Yoshihito Amemiya
2002	J	`jnl`	A CMOS Reaction-Diffusion Circuit Based on Cellular-Automaton Processing Emulating the Belousov-Zhabotinsky Reaction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tetsuya Asai, Yuusaku Nishimiya, Yoshihito Amemiya
2002	B	`conf`	A novel architecture for implementing large-scale Hopfield neural networks using CDMA communication technology. SMC Yusuke Kanazawa, Takashi Yamada, Tetsuya Asai, Yoshihito Amemiya
2000	—	`conf`	An Analog-Digital Hybrid CMOS Circuit for Two-Dimensional Motion Detection with Correlation Neural Networks. IJCNN (3) Tetsuya Asai, Masato Koutani, Yoshihito Amemiya
1998	—	`conf`	nu-MOS cellular-automaton devices for intelligent image sensors. KES (3) Masayuki Ikebe, Masamichi Akazawa, Yoshihito Amemiya
1994	J	`jnl`	An all-analog expandable neural network LSI with on-chip backpropagation learning. IEEE J. Solid State Circuits Takashi Morie, Yoshihito Amemiya
1992	J	`jnl`	A high-speed digital neural network chip with low-power chain-reaction architecture. IEEE J. Solid State Circuits Kuniharu Uchimura, Osamu Saito, Yoshihito Amemiya