Yoshihisa Fujimoto

12 papers Journal 5Unranked 7
YearRankTypeTitle / Venue / Authors
2009 J jnl
A 100 MS/s 4 MHz Bandwidth 70 dB SNR ΔΣ ADC in 90 nm CMOS.
IEEE J. Solid State Circuits
Yoshihisa Fujimoto, Yusuke Kanazawa, Pascal Lo Ré, Kunihiko Iizuka
2009 J jnl
Herman Rings of Blaschke Products of Degree 3.
Int. J. Bifurc. Chaos
Yoshihisa Fujimoto
2007 — conf
A 18 mW CT ΔΣ modulator with 25 MHz bandwidth for next generation wireless applications.
CICC
Xuefeng Chen, Yan Wang, Yoshihisa Fujimoto, Pascal Lo Ré, Yusuke Kanazawa, Jesper Steensgaard, Gabor C. Temes
2006 — conf
A 100-MS/s 4-MHz Bandwidth 77.3-dB SNDR ΔΣ ADC with a Triple Sampling Technique.
CICC
Yusuke Kanazawa, Yoshihisa Fujimoto, Pascal Lo Ré, Masayuki Miyamoto
2006 — conf
An 80/100MS/s 76.3/70.1dB SNDR ΔΣ ADC for Digital TV Receivers.
ISSCC
Yoshihisa Fujimoto, Yusuke Kanazawa, Pascal Lo Ré, Masayuki Miyamoto
2005 J jnl
A delta-sigma modulator for a 1-bit digital switching amplifier.
IEEE J. Solid State Circuits
Yoshihisa Fujimoto, Pascal Lo Ré, Masayuki Miyamoto
2004 — conf
A delta-sigma modulator for 1-bit digital switching amplifier [audio power amplifier].
CICC
Pascal Lo Ré, Yoshihisa Fujimoto, Hitoshi Tani, Masayuki Miyamoto
2004 J jnl
A low-power switched-capacitor variable gain amplifier.
IEEE J. Solid State Circuits
Yoshihisa Fujimoto, Hitoshi Tani, Masahiko Maruyama, Hiroyuki Akada, Hiroaki Ogawa, Masayuki Miyamoto
2003 — conf
A highly linear CMOS buffer circuit with an adjustable output impedance.
CICC
Masato Koutani, Yoshihisa Fujimoto, Masayuki Miyamoto
2003 — conf
A low power sample-and-hold amplifier.
ESSCIRC
Hitoshi Tani, Yoshihisa Fujimoto, Masahiko Maruyama, Hiroyuki Akada, Hiroaki Ogawa, Masayuki Miyamoto
2001 J jnl
CDMA functional blocks using recycling integrator correlators-matched filters and delay-locked loops.
IEEE J. Solid State Circuits
Kunihiko Iizuka, Masayuki Miyamoto, Yoshiji Ohta, Takahiro Suyama, Keita Hara, Shuichi Kawama, Hirofumi Matsui, Shin'ichiro Azuma, Shigenari Taguchi, Yoshihisa Fujimoto, Daniel Senderowicz
2000 — conf
A 2-V 3.7-mW delay locked-loop using recycling integrator correlators for a 5-Mcps DS-CDMA demodulator.
CICC
Yoshihisa Fujimoto, Shuichi Kawama, Kunihiko Iizuka, Masayuki Miyamoto, Daniel Senderowicz