Yoshihiko Horio

46 papers B 13C 6Misc 1Journal 10Unranked 16

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Analog VLSI Implementation of Subthreshold Spiking Neural Networks and Its Application to Reservoir Computing. IEEE Trans. Circuits Syst. I Regul. Pap. Satoshi Moriya, Masaya Ishikawa, Satoshi Ono, Hideaki Yamamoto, Yasushi Yuminaka, Yoshihiko Horio, Jordi Madrenas, Shigeo Sato
2025	J	`jnl`	Fractal memory structure in the spatiotemporal learning rule. Frontiers Comput. Neurosci. Takemori Orima, Ichiro Tsuda, Minoru Tsukada, Hiromichi Tsukada, Yoshihiko Horio
2024	B	`conf`	An event-driven mixed analog/digital spiking neural network circuit model for hippocampal spatiotemporal context learning and memory. IJCNN Takeru Tsuji, Takemori Orima, Yoshihiko Horio
2024	B	`conf`	Analysis of Learning Process of Synaptic Weights in Spatio-temporal Learning Networks for Hardware Implementation. IJCNN Takemori Orima, Yoshihiko Horio, Takeru Tsuji
2024	C	`conf`	Bifurcation phenomena observed from two-variable spiking neuron integrated circuit. ISCAS Takemori Orima, Yoshihiko Horio, Satoshi Moriya, Shigeo Sato
2024	B	`conf`	Design of Mixed-Signal LSI with Analog Spiking Neural Network and Digital Inference Circuits for Reservoir Computing. IJCNN Satoshi Moriya, Hideaki Yamamoto, Masaya Ishikawa, Yasushi Yuminaka, Yoshihiko Horio, Jordi Madrenas, Shigeo Sato
2023	—	`conf`	An Extended Spatiotemporal Contextual Learning and Memory Network Model for Hardware Implementation. INNS DLIA@IJCNN Takemori Orima, Takeru Tsuji, Yoshihiko Horio
2022	B	`conf`	A Fully Analog CMOS Implementation of a Two-variable Spiking Neuron in the Subthreshold Region and its Network Operation. IJCNN Satoshi Moriya, Hideaki Yamamoto, Shigeo Sato, Yasushi Yuminaka, Yoshihiko Horio, Jordi Madrenas
2022	J	`jnl`	Secret-Key Exchange Through Synchronization of Randomized Chaotic Oscillators Aided by Logistic Hash Function. IEEE Trans. Circuits Syst. I Regul. Pap. Koshiro Onuki, Kenichiro Cho, Yoshihiko Horio, Takaya Miyano
2021	—	`conf`	A Subthreshold Spiking Neuron Circuit Based on the Izhikevich Model. ICANN (5) Shigeo Sato, Satoshi Moriya, Yuka Kanke, Hideaki Yamamoto, Yoshihiko Horio, Yasushi Yuminaka, Jordi Madrenas
2021	—	`conf`	Design for 3-D Stacked Neural Network Circuit with Cyclic Analog Computing. 3DIC Koji Kiyoyama, Yoshihiko Horio, Takafumi Fukushima, Hiroyuki Hashimoto, Takemori Orima, Mitsumasa Koyanagi
2021	—	`conf`	Implementation of a Chaotic Neural Network Reservoir on a TSV/μBump Stacked 3D Cyclic Neural Network Integrated Circuit. 3DIC Yoshihiko Horio, Takemori Orima, Koji Kiyoyama, Mitsumasa Koyanagi
2019	—	`conf`	An Izhikevich Model Neuron MOS Circuit for Low Voltage Operation. ICANN (1) Yuki Tamura, Satoshi Moriya, Tatsuki Kato, Masao Sakuraba, Yoshihiko Horio, Shigeo Sato
2019	B	`conf`	Chaotic Neural Network Reservoir. IJCNN Yoshihiko Horio
2019	B	`conf`	Short-term Prediction of Hyperchaotic Flow Using Echo State Network. IJCNN Aren Sinozaki, Kota Shiozawa, Kazuki Kajita, Takaya Miyano, Yoshihiko Horio
2017	J	`jnl`	An Improved Parameter Value Optimization Technique for the Reflectionless Transmission-Line Model of the Cochlea. J. Robotics Netw. Artif. Life Takemori Orima, Yoshihiko Horio
2012	J	`jnl`	Beta encoders: Symbolic Dynamics and Electronic Implementation. Int. J. Bifurc. Chaos Tohru Kohda, Yoshihiko Horio, Yoichiro Takahashi, Kazuyuki Aihara
2011	—	`conf`	A CMOS nonlinear-map circuit array for threshold-coupled chaotic maps using pulse-modulation approach. ECCTD Takashi Morie, Daisuke Atuti, Kazuki Ifuku, Yoshihiko Horio, Kazuyuki Aihara
2011	—	`conf`	Forced chaos generator with switched CMOS active inductance. ECCTD Yusuke Tsubaki, Yoshihiko Horio, Kazuyuki Aihara
2010	—	`conf`	Mutual Information Analyses of Chaotic Neurodynamics Driven by Neuron Selection Methods in Synchronous Exponential Chaotic Tabu Search for Quadratic Assignment Problems. ICONIP (1) Tetsuo Kawamura, Yoshihiko Horio, Mikio Hasegawa
2009	C	`conf`	A Multi-hysteresis VCCS and its Application to Multi-scroll Chaotic Oscillators. ISCAS Kenya Jin'no, Yoshihiko Horio, Ryosuke Domae, Kazuyuki Aihara
2009	C	`conf`	Adaptive Feedback Control of Chaotic Neurodynamics in Analog Circuits. ISCAS Hiroyasu Ando, Aki Nakano, Yoshihiko Horio, Kazuyuki Aihara
2009	J	`jnl`	Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yoshihiko Horio
2007	—	`conf`	An IC implementation of a hysteresis two-port VCCS chaotic oscillator. ECCTD Takuya Hamada, Yoshihiko Horio, Kazuyuki Aihara
2005	J	`jnl`	A mixed analog/digital chaotic neuro-computer system for quadratic assignment problems. Neural Networks Yoshihiko Horio, Tohru Ikeguchi, Kazuyuki Aihara
2005	J	`jnl`	An asynchronous spiking chaotic neuron integrated circuit. Neurocomputing Yoshihiko Horio, Takuya Taniguchi, Kazuyuki Aihara
2005	B	`conf`	Improved chaotic neuro-computer with output-coding for quadratic assignment problems. IJCNN Koji Mon, Yoshihiko Horio, Kazuyuki Aihara
2005	—	`conf`	One-dimensional discrete-time dynamical systems circuit using floating-gate MOS peaking current sink/source. ECCTD Tomoumi Yagasaki, Yoshihiko Horio, Kazuyuki Aihara
2004	B	`conf`	Chaotic neuro-computer prototype for quadratic assignment problems. IJCNN Koji Mori, Takahide Okuno, Yoshihiko Horio
2004	B	`conf`	Exponential chaotic tabu search hardware for quadratic assignment problems using switched-current chaotic neuron IC. IJCNN Satoshi Matsui, Yukihiro Kobayashi, Kentaro Watanabe, Yoshihiko Horio
2004	B	`conf`	Mixed analog/digital chaotic neuro-computer prototype: 400-neuron dynamical associative memory. IJCNN Yoshihiko Horio, Takahide Okuno, Koji Mori
2004	B	`conf`	Switched-Capacitor Large-Scale Chaotic Neuro-Computer Prototype and Chaotic Search Dynamics. KES Yoshihiko Horio, Takahide Okuno, Koji Mori
2003	—	`conf`	An integrated multi-scroll circuit with floating-gate MOSFETs. ISCAS (3) Tetsuya Fujiwara, Yoshihiko Horio, Kazuyuki Aihara
2003	B	`conf`	Integrated pulse neuron circuit for asynchronous pulse neural networks. IJCNN Takuya Taniguchi, Yoshihiko Horio, Kazuyuki Aihara
2003	B	`conf`	Mixed analog/digital system for quadratic assignment problems. IJCNN Yukihiro Kohayashi, Takehiko Koyama, Satoshi Matsui, Yoshihiko Horio, Kazuyuki Aihara
2003	J	`jnl`	Neuron-synapse IC chip-set for large-scale chaotic neural networks. IEEE Trans. Neural Networks Yoshihiko Horio, Kazuyuki Aihara, O. Yamamoto
2001	—	`conf`	A simulated LC oscillator using multi-input floating-gate MOSFETS. ISCAS (3) Kinya Matsuda, Yoshihiko Horio, Kazuyuki Aihara
2001	—	`conf`	Influences of anti-aliasing filter on estimation of the largest Lyapunov exponent. ISCAS (3) Shinya Nagata, Yoshihiko Horio
1999	—	`conf`	Switched-capacitor multi-internal-state chaotic neuron circuit with unipolar and bipolar output functions. ISCAS (5) Yoshihiko Horio, Izumi Kobayashi, Masato Kawakami, Hiroshi Hayashi, Kazuyuki Aihara
1998	—	`conf`	An asynchronous pulse neural network model and its analog IC implementation. ICECS Yoshihiko Horio, Hidekazu Yasuda, Mitsuru Hanagata, Kazuyuki Aihara
1996	J	`jnl`	Subadaptive piecewise linear quantization for speech signal (64 kbit/s) compression. IEEE Trans. Speech Audio Process. Hiroto Saito, Isao Umoto, Akira Sasou, Shogo Nakamura, Yoshihiko Horio, Tahiro Kubota
1995	C	`conf`	Dynamic Associative Memory Using Switched-Capacitor Chaotic Neurons. ISCAS Yoshihiko Horio, Ken Suyama
1995	—	`conf`	Switched-current chaotic neural network with chaotic simulated annealing. ICNN Nobuo Kanou, Yoshihiko Horio
1994	C	`conf`	IC Implementation of Switched-Capacitor Chaotic Neuron. ISCAS Yoshihiko Horio, Ken Suyama
1993	C	`conf`	Switched-capacitor Chaotic Neuron for Chaotic Neural Networks. ISCAS Yoshihiko Horio, Ken Suyama
1991	Misc	`conf`	A simple method for designing a hierarchical structure transversal filter. ICASSP Akiyoshi Kawahashi, Shogo Nakanura, Yoshihiko Horio, Yukio Kadowaki