Yoshihide Komatsu

12 papers Journal 8Unranked 4

Year	Rank	Type	Title / Venue / Authors
2021	—	`conf`	Investigation of the Failure Mechanism of InGaAs-pHEMT under High Temperature Operating Life Tests. IRPS Yasunori Tateno, Ken Nakata, Akio Oya, Keita Matsuda, Yoshihide Komatsu, Shinichi Osada, Masafumi Hirata, Shigeyuki Ishiyama, Toshiki Yoda, Atsushi Nitta, Tomio Sato
2020	J	`jnl`	A 0.6-V Adaptive Voltage Swing Serial Link Transmitter Using Near Threshold Body Bias Control and Jitter Estimation. IEICE Trans. Electron. Yoshihide Komatsu, Akinori Shinmyo, Mayuko Fujita, Tsuyoshi Hiraki, Kouichi Fukuda, Noriyuki Miura, Makoto Nagata
2019	J	`jnl`	A 0.25-27-Gb/s PAM4/NRZ Transceiver With Adaptive Power CDR and Jitter Analysis. IEEE J. Solid State Circuits Yoshihide Komatsu, Akinori Shinmyo, Shuji Kato, Masami Funabashi, Kazuya Hatooka, Mayuko Fujita, Kenji Tanaka, Aoi Yamasaki, Kouichi Fukuda
2018	—	`conf`	A 0.25-27Gb/s Wideband PAM4/NRZ Transceiver with Adaptive Power CDR for 8K System. A-SSCC Yoshihide Komatsu, Akinori Shinmyo, Masami Funabashi, Shuji Kato, Kazuya Hatooka, Kenji Tanaka, Mayuko Fujita, Kouichi Fukuda
2011	J	`jnl`	An Ultra-Wide Range Bi-Directional Transceiver With Adaptive Power Control Using Background Replica VCO Gain Calibration. IEEE J. Solid State Circuits Tsuyoshi Ebuchi, Yoshihide Komatsu, Masatomo Miura, Tomoko Chiba, Toru Iwata, Shiro Dosho, Takefumi Yoshikawa
2009	J	`jnl`	A 125-1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration. IEEE J. Solid State Circuits Tsuyoshi Ebuchi, Yoshihide Komatsu, Tatsuo Okamoto, Yukio Arima, Yuji Yamada, Kazuaki Sogawa, Kouji Okamoto, Takashi Morie, Takashi Hirata, Shiro Dosho, Takefumi Yoshikawa
2008	J	`jnl`	Transceiver Macro with Spread-Spectrum Clocking Capability for AC-Coupled Cable Interfaces. IEICE Trans. Electron. Takefumi Yoshikawa, Yoshihide Komatsu, Tsuyoshi Ebuchi, Takashi Hirata
2007	J	`jnl`	Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias. IEICE Trans. Electron. Yoshihide Komatsu, Koichiro Ishibashi, Makoto Nagata
2006	J	`jnl`	Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond. IEICE Trans. Electron. Koichiro Ishibashi, Tetsuya Fujimoto, Takahiro Yamashita, Hiroyuki Okada, Yukio Arima, Yasuyuki Hashimoto, Kohji Sakata, Isao Minematsu, Yasuo Itoh, Haruki Toda, Motoi Ichihashi, Yoshihide Komatsu, Masato Hagiwara, Toshiro Tsukada
2006	J	`jnl`	Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond. IEICE Trans. Electron. Yoshihide Komatsu, Yukio Arima, Koichiro Ishibashi
2005	—	`conf`	Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias. CICC Yoshihide Komatsu, Koichiro Ishibashi, Masaharu Yamamoto, Toshiro Tsukada, Kenji Shimazaki, Mitsuya Fukazawa, Makoto Nagata
2004	—	`conf`	A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond. CICC Yoshihide Komatsu, Yukio Arima, Tetsuya Fujimoto, Takahiro Yamashita, Koichiro Ishibashi