Yoonjae Choi

35 papers C 1Journal 28Unranked 6
YearRankTypeTitle / Venue / Authors
2026 — conf
37.3 A 2nm All-Digital 14.4Gb/s/pin LPDDR6 PHY with Quarter-Rate Clocking Architecture and Multi-Level FIFO-Based Speculative DFE.
ISSCC
Yoonjae Choi, Daero Kim, Myunggon Kim, Sangmin Lee, Hansol Kang, Gwangwon Lee, Yoonhyung Kim, Sungsik Kang, Hyun Cho, Boyoung Kang, Kyoungwon Lee, Jaegeun Song, Jinho Choi, Shinyoung Yi, Billy Koo, Kwanyeob Chae, Hyo-Gyuem Rhew
2026 J jnl
A 15-Gb/s PAM-3 Transceiver With Hybrid Equalization and Time-Domain Decoder for High-Bandwidth-Memory Interfaces.
IEEE J. Solid State Circuits
Hwaseok Shin, Yoonjae Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Junseob So, Seon-Been Lee, Taehwan Kim, Chulwoo Kim
2025 J jnl
A 28-Gb/s Single-Ended PAM-4 Transceiver With Active-Inductor Equalizer and Amplitude- Detection LSB Decoder for Memory Interfaces.
IEEE Trans. Very Large Scale Integr. Syst.
Hwaseok Shin, Hyoshin Kang, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Junseob So, Taehwan Kim, Chulwoo Kim
2025 J jnl
A 52-Gb/s Low-Power PAM-4 Baud-Rate CDR Using Pattern-Based Phase Detector for Short-Reach Applications.
IEEE J. Solid State Circuits
Seungwoo Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Hyunsu Park, Youngwook Kwon, Changmin Sim, Seongcheol Kim, Chulwoo Kim
2024 J jnl
A 0.45 pJ/b 24 Gb/s NRZ Receiver Data-Path Using Half-Baud-Rate Duobinary Sampling.
IEEE Trans. Circuits Syst. II Express Briefs
Seungwoo Park, Yoonjae Choi, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Changmin Sim, Seongcheol Kim, Chulwoo Kim
2024 J jnl
A 10-Gb/s Wireline Receiver Using Linear Baud-Rate CDR and Analog Equalizer for Free Space Optical Communication Over 10- and 100-m Distances.
IEEE J. Solid State Circuits
Jincheol Sim, Changmin Sim, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Jong-Min Kim, Ju-Hyung Lee, Young-Chai Ko, Chulwoo Kim
2024 J jnl
A 13-Gb/s Single-Ended NRZ Receiver With 1-Sample Per 2-UI Using Data Edge Sampling for Memory Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs
Hyoshin Kang, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Chulwoo Kim
2024 J jnl
A 25-Gb/s Single-Ended PAM-4 Transmitter With iPWM-Based FFE and RLM-Matched Voltage-Mode Driver for High-Speed Memory Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yoonjae Choi, Changmin Sim, Jonghyuck Choi, Jincheol Sim, Hyunsu Park, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Chulwoo Kim
2024 J jnl
A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection.
IEEE J. Solid State Circuits
Kwanyeob Chae, Jaegeun Song, Yoonjae Choi, Jiyeon Park, Billy Koo, Jihun Oh, Shinyoung Yi, Won Lee, Dongha Kim, Kyeongkeun Kang, Eunsu Kim, Juyoung Kim, Sanghune Park, Sungcheol Park, Mijung Noh, Hyo Gyuem Rhew, Jongshin Shin
2024 — conf
A 4-nm 9.6-Gb/s/pin LPDDR5X PHY With Adaptive Driver Strength Control and Fast Periodic Training for Full DVFS DRAM.
A-SSCC
Yoonjae Choi, Jaegeun Song, Daero Kim, Myunggon Kim, Jiyeon Park, Jinho Choi, Changki Kwon, Minho Seo, Jihun Oh, Shinyoung Yi, Billy Koo, Kwanyeob Chae, Jongshin Shin
2024 J jnl
A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for Memory Interfaces.
IEEE J. Solid State Circuits
Jonghyuck Choi, Yoonjae Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Chulwoo Kim
2024 J jnl
Single-Ended PAM-4 Transmitters With Data Bus Inversion and ZQ Calibration for High-Speed Memory Interfaces.
IEEE J. Solid State Circuits
Seongcheol Kim, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Changmin Sim, Junseob So, Taehyeong Park, Chulwoo Kim
2023 — conf
A 0.83pJ/b 52Gb/s PAM-4 Baud-Rate CDR with Pattern-Based Phase Detector for Short-Reach Applications.
ISSCC
Seungwoo Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Hyunsu Park, Youngwook Kwon, Chulwoo Kim
2023 J jnl
A 15-Gb/s Single-Ended NRZ Receiver Using Self-Referenced Technique With 1-Tap Latched DFE for DRAM Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs
Seongcheol Kim, Jincheol Sim, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, Chulwoo Kim
2023 J jnl
A 16-Gb/s NRZ Receiver With 0.0019-pJ/bit/dB 1-Tap Charge-Redistribution DFE.
IEEE Trans. Circuits Syst. II Express Briefs
Jonghyuck Choi, Yoonjae Choi, Hyunsu Park, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Chulwoo Kim
2023 J jnl
A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces.
IEEE J. Solid State Circuits
Yoonjae Choi, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Chulwoo Kim
2023 J jnl
A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces.
IEEE J. Solid State Circuits
Youngwook Kwon, Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Seungwoo Park, Kyeong-Min Kim, Changkyu Choi, Hae-Kang Jung, Chulwoo Kim
2023 J jnl
A 4-GHz Ring-Oscillator-Based Digital Sub-Sampling PLL With Energy-Efficient Dual-Domain Phase Detector.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yoonjae Choi, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Changmin Sim, Chulwoo Kim
2023 J jnl
PAM-4 Receiver With 1-Tap DFE Using Clocked Comparator Offset Instead of Threshold Voltages for Improved LSB BER Performance.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jincheol Sim, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Chulwoo Kim
2022 — conf
A 0.385-pJ/bit 10-Gb/s TIA-Terminated Di-Code Transceiver with Edge-Delayed Equalization, ECC, and Mismatch Calibration for HBM Interfaces.
ISSCC
Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Junyoung Song, Chulwoo Kim
2022 J jnl
A 15 Gb/s Non-Return-to-Zero Transmitter With 1-Tap Pre-Emphasis Feed-Forward Equalizer for Low-Power Ground Terminated Memory Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs
Youngwook Kwon, Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Seungwoo Park, Chulwoo Kim
2022 J jnl
A 2.4-8 GHz Phase Rotator Delay-Locked Loop Using Cascading Structure for Direct Input-Output Phase Detection.
IEEE Trans. Circuits Syst. II Express Briefs
Hyunsu Park, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Chulwoo Kim
2022 J jnl
A 25 Gb/s Wireline Receiver With Feedforward and Feedback Equalizers at Analog Front-End.
IEEE Trans. Circuits Syst. II Express Briefs
Jincheol Sim, Yeonho Lee, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, Chulwoo Kim
2022 C conf
A 266-3750 MHz Wide-Range Adaptive Phase-Rotator-Based All Digital DLL for LPDDR5 Controllers.
ISCAS
Jeewan Lee, Yoonjae Choi, Chulwoo Kim
2022 J jnl
A 56-Gb/s PAM-4 Receiver Using Time-Based LSB Decoder and S/H Technique for Robustness to Comparator Voltage Variations.
IEEE J. Solid State Circuits
Hyunsu Park, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Chulwoo Kim
2022 J jnl
Analysis of a Multiwire, Multilevel, and Symbol Correlation Combination Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jonghyuck Choi, Yoonjae Choi, Hyunsu Park, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Chulwoo Kim
2021 J jnl
30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links.
IEEE J. Solid State Circuits
Hyunsu Park, Junyoung Song, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Jeongsik Yoo, Chulwoo Kim
2021 J jnl
A 0.99-pJ/b 15-Gb/s Counter-Based Adaptive Equalizer Using Single Comparator in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Yoonjae Choi, Yeonho Lee, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Chulwoo Kim
2021 J jnl
A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line.
IEEE J. Solid State Circuits
Hyunsu Park, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Gyutae Park, Jinil Chung, Kyeong-Min Kim, Hae-Kang Jung, Hyungsoo Kim, Junhyun Chun, Chulwoo Kim
2021 J jnl
A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector.
IEEE Access
Yoonjae Choi, Sewook Hwang, Yeonho Lee, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Chulwoo Kim
2019 J jnl
12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces.
IEEE J. Solid State Circuits
Yeonho Lee, Yoonjae Choi, Junyoung Song, Sewook Hwang, Sang-Geun Bae, Jaehun Jun, Chulwoo Kim
2018 — conf
12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interface.
ASP-DAC
Yeonho Lee, Yoonjae Choi, Chulwoo Kim
2018 J jnl
A Low-Power Post-LPDDR4 Interface Using AC Termination at RX and an Active Inductor at TX.
IEEE Trans. Circuits Syst. II Express Briefs
Jeongsik Yoo, Yeonho Lee, Yoonjae Choi, Hyunsu Park, Sanghune Park, Chulwoo Kim
2017 — conf
29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces.
ISSCC
Yeonho Lee, Yoonjae Choi, Sang-Geun Bae, Jaehun Jun, Junyoung Song, Sewook Hwang, Chulwoo Kim
2013 J jnl
Extracting Events from Web Documents for Social Media Monitoring Using Structured SVM.
IEICE Trans. Inf. Syst.
Yoonjae Choi, Pum-Mo Ryu, Hyunki Kim, Changki Lee