Yongzhen Chen - RankMe

61 papers C 9Journal 15Unranked 37

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 70-Gb/s PAM-4 wireline transmitter with dynamic-bias-based pre-emphasis in 28-nm CMOS. Microelectron. J. Junkun Chen, Youzhi Gu, Miaomiao Xu, Yangxin Xiang, Yongzhen Chen, Cuixia Wang, Jiangfeng Wu
2026	J	`jnl`	A high-linearity sub-6 GHz programmable-gain push-pull driver power amplifier utilizing dual-loop biasing. Microelectron. J. Minghao Jiang, Weibo Li, Tianshuo Xie, Yongzhen Chen, Jiangfeng Wu
2025	J	`jnl`	A 16-bit 1-MS/s SAR ADC With Capacitor Mismatch Self-Calibration. IEEE Trans. Very Large Scale Integr. Syst. Jie Ding, Fuming Liu, Kuan Deng, Zihan Zheng, Jingnan Zheng, Yongzhen Chen, Jiangfeng Wu
2025	C	`conf`	A Rapid Binary Search-Based Capacitor Mismatch Calibration Algorithm. ISCAS Yifei Bai, Huajun Yao, Fengyi Mei, Cuixia Wang, Yongzhen Chen, Jiangfeng Wu
2025	J	`jnl`	An Area-Efficient High-Precision Analog Front End for Battery Management System. IEEE Trans. Circuits Syst. II Express Briefs Kuan Deng, Jie Ding, Jingnan Zheng, Yongzhen Chen, Jiangfeng Wu
2025	J	`jnl`	Multiband Reconfigurable Broadband Transmitter Supporting 5G New Radio. IEEE Trans. Very Large Scale Integr. Syst. Minghao Jiang, Tianshuo Xie, Weibo Li, Yangxin Xiang, Yongzhen Chen, Jiangfeng Wu
2025	J	`jnl`	Underwater-Image Enhancement Based on Maximum Information-Channel Correction and Edge-Preserving Filtering. Symmetry Wei Liu, Jingxuan Xu, Siying He, Yongzhen Chen, Xinyi Zhang, Hong Shu, Ping Qi
2024	J	`jnl`	A 0.5-V 0.02% THD Bulk-Driven OTA for Continuous-Time Applications in 180 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Yangxin Xiang, Huajun Yao, Minghao Jiang, Junkun Chen, Yongzhen Chen, Jiangfeng Wu
2024	—	`conf`	A 40Gb/s Multi-band Wireline Receiver Analog Front-end for 50.4dB Channel Loss Compensation. MWSCAS Mingzhe Liu, Yongzhen Chen, Jiangfeng Wu, Cuixia Wang
2024	—	`conf`	A BJT-Based Temperature Sensor Achieving an Inaccuracy of ±0.3°C (3σ) and a 6.605 pJ∙K APCCAS Chenyang Han, Yujun Shu, Tianwei Li, Jiangfeng Wu, Yongzhen Chen
2024	J	`jnl`	A Foreground Wide-Band Receiver I/Q Mismatch Calibration Method in FDD Transceiver. IEEE Trans. Circuits Syst. I Regul. Pap. Huajun Yao, Yangxin Xiang, Yongzhen Chen, Jiangfeng Wu
2024	J	`jnl`	Design and Implementation of an EMI-Immune Daisy Chain Interface With a PID-Based CDR Algorithm for Battery Management System Communication. IEEE Access Zihan Zheng, Yongzhen Chen, Jie Ding, Xinhao Xu, Kuan Deng, Yangxin Xiang, Weibo Li, Jiangfeng Wu
2023	—	`conf`	A 32GS/s 7bit TI-SAR ADC in 28nm for 32Gb/s ADC-Based SerDes Receiver. ASICON Jun Chen, Fengyi Mei, Mingzhe Liu, Yongzhen Chen, Jiangfeng Wu
2023	C	`conf`	A 4.75-64 Gb/s PAM-4 Wireline Transmitter with 3-tap FFE in 28-nm CMOS. ISCAS Junkun Chen, Youzhi Gu, Miaomiao Xu, Yongzhen Chen, Cuixia Wang, Jiangfeng Wu
2023	C	`conf`	A Foreground LSB-Based Capacitor Mismatch Calibration Method in An 18-bit SAR ADC. ISCAS Jie Ding, Yongzhen Chen, Cuixia Wang, Jiangfeng Wu
2023	—	`conf`	A Low-power Digital Automatic Gain Control Design in Wireless Communication Receivers. ASICON Jiangshan Zhao, Jiankun Huang, Yongzhen Chen, Jiangfeng Wu
2023	C	`conf`	A Wideband Receiver I/Q Mismatch Calibration Method in FDD Transceiver. ISCAS Huajun Yao, Yangxin Xiang, Yongzhen Chen, Cuixia Wang, Jiangfeng Wu
2023	—	`conf`	A low-power daisy-chain controller implemention in BMS based on power mode switching. ASICON Xinhao Xu, Yongzhen Chen, Jiangfeng Wu
2023	—	`conf`	Complexity-Reduced Joint Calibration for Nonlinearity and I/Q Imbalance in Direct-Conversion Transmitters. ASICON Weibo Li, Minghao Jiang, Yongzhen Chen, Jiangfeng Wu
2023	—	`conf`	Nonlinear modeling of MIMO antenna array power amplifiers based on time-delay neural network. ASICON Yiwei Zhou, Weibo Li, Yongzhen Chen
2023	—	`conf`	Pipelined-SAR ADC Calibration Technique Based on Gain-Bit Weights. ASICON Hang Ling, Yifei Bai, Fengyi Mei, Huajun Yao, Yongzhen Chen, Jiangfeng Wu
2023	J	`jnl`	Research on monaural speech segregation based on feature selection. EURASIP J. Audio Speech Music. Process. Xiaoping Xie, Yongzhen Chen, Rufeng Shen, Dan Tian
2022	—	`conf`	0.7-6 GHz Programable Gain Push-Pull Driver PA Based on Dual-Loop Biases. APCCAS Minghao Jiang, Chenyang Han, Weibo Li, Jiangfeng Wu, Yongzhen Chen
2022	C	`conf`	A 2.5-GS/s Time-Interleaved SAR-Assisted Ringamp-Based Pipelined ADC with Digital Background Calibration. ISCAS Jingchao Lan, Danfeng Zhai, Yongzhen Chen, Zhekan Ni, Xingchen Shen, Fan Ye, Junyan Ren
2022	—	`conf`	A 64Gb/s PAM-4 Digital Equalizer With Tap-Configurable FFE and Partially Unrolled DFE in 28nm CMOS. ICTA Xinjie Feng, Yongzhen Chen, Youzhi Gu, Jiangfeng Wu
2022	—	`conf`	A Current-Mode, 30 dB Range with 0.5 dB Step, 0.1 to 6 GHz Attenuator for Wideband Receiver. MWSCAS Yangxin Xiang, Chenyang Han, Cuixia Wang, Jiangfeng Wu, Yongzhen Chen
2022	J	`jnl`	Effective Gain Analysis and Statistic Based Calibration for Ring Amplifier With Robustness to PVT Variation. IEEE Trans. Circuits Syst. II Express Briefs Jingchao Lan, Yongzhen Chen, Xingchen Shen, Zhekan Ni, Yimin Wu, Fan Ye, Junyan Ren
2022	—	`conf`	Feature Matching for Indoor-Oriented Visual Odometry. NaNA Xinghui Zhu, Yongzhen Chen, Xiaodong Zhang, Zhiwei Zhang, Baoquan Ren
2021	—	`conf`	A 161mW 32Gb/s ADC-Based NRZ SerDes Receiver Front End in 28nm. ICTA Runze Chi, Junkun Chen, Youzhi Gu, Jiangfeng Wu, Yongzhen Chen
2021	—	`conf`	A 2-GS/s 200-MHz BW Oversampling Continuous-Time Pipeline ADC with Adaptive Digital Filter in 28nm. ICTA Liran Dong, Yujun Shu, Yongzhen Chen, Jiangfeng Wu
2021	—	`conf`	A 32Gb/s NRZ Wireline Transmitter with CMFB- Based CML Driver in 28nm CMOS Technology. MWSCAS Youzhi Gu, Junkun Chen, Xiaolin Li, Yongzhen Chen, Jiangfeng Wu
2021	—	`conf`	A 6-bit Active Phase Shifter with Quadrature Outputs. ASICON Yujie Wu, Gang Zhang, Yongzhen Chen, Jiangfeng Wu
2021	—	`conf`	A 71dB DC Gain, 0.1% THD, 0.5-V Bulk-Driven Class-AB OTA Achieved by Novel CMFB Methods. MWSCAS Yangxin Xiang, Saisai Jin, Yongzhen Chen, Jiangfeng Wu
2021	J	`jnl`	A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Yuefeng Cao, Shumin Zhang, Tianli Zhang, Yongzhen Chen, Yutong Zhao, Chixiao Chen, Fan Ye, Junyan Ren
2021	—	`conf`	A High-Performance Mel-scale Frequency Cepstral Coefficients Digital Circuit Used on Keyword-Spotting Chip. ASICON Jiankun Huang, Xinjie Feng, Congying Zhou, Yongzhen Chen
2021	—	`conf`	An Input Buffer for 4 GS/s 14-b Time-Interleaved ADC. ASICON Li Zhang, Yunchuan Wang, Fengyi Mei, Yongzhen Chen, Jiangfeng Wu
2021	—	`conf`	Digital Calibration of Capacitor Mismatch and Gain Error in Pipelined SAR ADCs. ASICON Yunchuan Wang, Li Zhang, Fengyi Mei, Yongzhen Chen, Jiangfeng Wu
2021	—	`conf`	Physical Coding Sublayer For 32Gbps SerDes Based On JESD204C. ASICON Xiaozhe Wang, Lingzhi Su, Xiyuan Du, Yongzhen Chen, Jiangfeng Wu
2019	—	`conf`	A 625MS/s, 12-Bit, SAR Assisted Pipeline ADC with Effective Gain Analysis for Inter-stage Ringamps. ESSCIRC Yongzhen Chen, Xingchen Shen, Zhekan Ni, Jingchao Lan, Chixiao Chen, Fan Ye, Junyan Ren
2019	J	`jnl`	A 7.8 fJ/conversion-step 9-bit 400-MS/s single-channel SAR ADC with fast control logic. Microelectron. J. Zhekan Ni, Yongzhen Chen, Fan Ye, Junyan Ren
2019	—	`conf`	A Double-Latch Comparator for Multi-GS/s SAR ADCs in 28nm CMOS. ASICON Pingshun Ma, Yongzhen Chen, Jiangfeng Wu
2019	—	`conf`	An Area-Efficient Multi-Rate Digital Decimator. ASICON Qi Li, Yujun Shu, Yongzhen Chen, Jiangfeng Wu
2019	—	`conf`	High Linear Ring Amplifier Design with Analysis on Settling Procedures. ASICON Yongzhen Chen, Jiangfeng Wu
2018	C	`conf`	A 100MS/S 12-bit Coarse-Fine SAR ADC with Shared Split-CDAC. ISCAS Manxin Li, Yongzhen Chen, Fan Ye, Junyan Ren
2018	—	`conf`	A 12-Bit ENOB 8MHz BW Noise-Shaping SAR ADC Using High-Speed Switches. MWSCAS Zhiyuan Dai, Hang Hu, Yongzhen Chen, Fan Ye, Junyan Ren
2018	—	`conf`	A 7.8 fJ/conversion-step 9-bit 400-MS/s single-channel SAR ADC with fast control logic. APCCAS Zhekan Ni, Yongzhen Chen, Fan Ye, Junyan Ren
2018	C	`conf`	A 800 MS/s, 12-Bit, Ringamp-Based SAR assisted Pipeline ADC with Gain Error Cancellation. ISCAS Yongzhen Chen, Zhekan Ni, Yuefeng Cao, Fan Ye, Junyan Ren
2018	J	`jnl`	A Time-Interleaved SAR Assisted Pipeline ADC With a Bias-Enhanced Ring Amplifier. IEEE Trans. Circuits Syst. II Express Briefs Yongzhen Chen, Jingjing Wang, Hang Hu, Fan Ye, Junyan Ren
2018	—	`conf`	An 11b 80MS/s SAR ADC With Speed-Enhanced SAR Logic and High-Linearity CDAC. APCCAS Yuefeng Cao, Yongzhen Chen, Zhekan Ni, Fan Ye, Junyan Ren
2018	J	`jnl`	An 8.2 fJ/conversion-step 9-bit 135 MS/s SAR ADC with redundant methods for acceleration. Microelectron. J. Yongzhen Chen, Fan Ye, Junyan Ren
2018	C	`conf`	An Operational Amplifier Assisted Input Buffer and An Improved Bootstrapped Switch for High-Speed and High-Resolution ADCs. ISCAS Yuefeng Cao, Tianli Zhang, Yongzhen Chen, Fan Ye, Junyan Ren
2017	C	`conf`	A 200MS/s, 11 bit SAR-assisted pipeline ADC with bias-enhanced ring amplifier. ISCAS Yongzhen Chen, Jingjing Wang, Hang Hu, Fan Ye, Junyan Ren
2017	—	`conf`	A background time-skew calibration technique in flash-assisted time-interleaved SAR ADCs. ASICON Yongzhen Chen, Yimin Wu, Fubiao Cao, Fan Ye, Junyan Ren
2017	—	`conf`	A proved dither-injection method for memory effect in double sampling pipelined ADC. ASICON Fubiao Cao, Yongzhen Chen, Yuefeng Cao, Fan Ye, Junyan Ren
2017	—	`conf`	A stacked-packaged 16-channel ADC for ultrasound application. ASICON Yimin Wu, Yongzhen Chen, Manxin Li, Fan Ye, Junyan Ren
2017	—	`conf`	An improved ring amplifier with process- and supply voltage-insensitive dead-zone. MWSCAS Yuefeng Cao, Yongzhen Chen, Tianli Zhang, Fan Ye, Junyan Ren
2017	—	`conf`	An input buffer for 12bit 2GS/s ADC. ASICON Fubiao Cao, Yongzhen Chen, Zhiyuan Dai, Fan Ye, Junyan Ren
2015	—	`conf`	A 1.5-GS/s 5-bit interpolating ADC with offset averaging and interpolating sharing resistors network. ASICON Rongjin Xu, Yongzhen Chen, Mingshuo Wang, Ning Li, Fan Ye, Junyan Ren
2015	—	`conf`	A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system. ESSCIRC Shunli Ma, Guangyao Zhou, Jianbing Jiang, Chixiao Chen, Yongzhen Chen, Fan Ye, Junyan Ren
2013	—	`conf`	A 12-bit 200-MS/s sample-and-hold amplifier with a hybrid Miller-Feedforward compensation technique. ASICON Yongzhen Chen, Chixiao Chen, Qiang Zhang, Fan Ye, Junyan Ren
2013	—	`conf`	sAES: A high throughput and low latency secure cloud storage with pipelined DMA based PCIe interface. FPT Yongzhen Chen, Miguel Rodel Felipe, Yi Wang, Yajun Ha, Shu Qin Ren, Khin Mi Mi Aung