Yongsun Lee

29 papers Journal 13Unranked 16
YearRankTypeTitle / Venue / Authors
2026 — conf
15.6 A 36GB 3.3TB/S HBM4 DRAM with Per-Channel TSV RDQS Auto Calibration and Fully-Programmable MBIST.
ISSCC
Sunghwan Joo, Jinyeon Kim, Yongsun Lee, Ji-Young Kim, Youngsik Lee, Yong-Min Kim, Chi Sung Oh, Kyu-Ha Shim, Haesuk Lee, Young-Yong Byun, Changhyun Bae, Joohwan Kim, Je-Min Ryu, Shin-Haeng Kang, Jaehoon Lee, Young-Uk Chang, Jaekyung Lee, Jong Tae Hwang, Daehwan Seo, Ki-Heon Na, Young Guen Song, Daihyun Lim, Kyung-Soo Ha, Young-Soo Sohn, Sangjoon Hwang
2024 J jnl
Reinforcement Learning Optimizes Power Dispatch in Decentralized Power Grid.
CoRR
Yongsun Lee, Hoyun Choi, Laurent Pagnier, Cook Hyun Kim, Jongshin Lee, Bukyoung Jhun, Heetae Kim, Jürgen Kurths, B. Kahng
2022 — conf
A Functional Verification Study of Quantum Key Distribute Networks and Services with a Trusted Node applied in KOREN.
ICTC
Sang-Kil Park, Yongsun Lee, Younseo Jeong, Jung Jin Ju, Ki-Dong Nam, Seongsu Park
2022 J jnl
A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM.
IEEE J. Solid State Circuits
Chanwoong Hwang, Hangi Park, Yongsun Lee, Taeho Seong, Jaehyouk Choi
2021 — conf
32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique.
ISSCC
Juyeop Kim, Yongwoo Jo, Younghyun Lim, Taeho Seong, Hangi Park, Seyeon Yoo, Yongsun Lee, Seojin Choi, Jaehyouk Choi
2021 — conf
A 365fsrms-Jitter and -63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third- Order Nonlinearity Cancelation and a Probability-Density-Shaping Δ ΣM.
ISSCC
Hangi Park, Chanwoong Hwang, Taeho Seong, Yongsun Lee, Jaehyouk Choi
2021 J jnl
A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator.
IEEE J. Solid State Circuits
Seyeon Yoo, Seojin Choi, Yongsun Lee, Taeho Seong, Younghyun Lim, Jaehyouk Choi
2020 — conf
17.1 A -240dB-FoMjitter and -115dBc/Hz PN @ 100kHz, 7.7GHz Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction.
ISSCC
Yongsun Lee, Taeho Seong, Jeonghyun Lee, Chanwoong Hwang, Hangi Park, Jaehyouk Choi
2020 — conf
17.3 A -58dBc-Worst-Fractional-Spur and -234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word.
ISSCC
Taeho Seong, Yongsun Lee, Chanwoong Hwang, Jeonghyun Lee, Hangi Park, Kyuho Jason Lee, Jaehyouk Choi
2019 — conf
A 140fsrms-Jitter and -72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator.
ISSCC
Seyeon Yoo, Seojin Choi, Yongsun Lee, Taeho Seong, Younghyun Lim, Jaehyouk Choi
2019 J jnl
A 320-fs RMS Jitter and - 75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC.
IEEE J. Solid State Circuits
Taeho Seong, Yongsun Lee, Seyeon Yoo, Jaehyouk Choi
2019 — conf
A 76fsrms Jitter and -40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization.
ISSCC
Juyeop Kim, Heein Yoon, Younghyun Lim, Yongsun Lee, Yoonseo Cho, Taeho Seong, Jaehyouk Choi
2019 J jnl
An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114.
IEEE J. Solid State Circuits
Seojin Choi, Seyeon Yoo, Yongsun Lee, Yongwoo Jo, Jeonghyun Lee, Younghyun Lim, Jaehyouk Choi
2019 J jnl
An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators.
IEEE J. Solid State Circuits
Juyeop Kim, Younghyun Lim, Heein Yoon, Yongsun Lee, Hangi Park, Yoonseo Cho, Taeho Seong, Jaehyouk Choi
2018 — conf
153 FSRMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHZ Ring-LC-Hybrid Injection-Locked Clock Multiplier.
VLSI Circuits
Seojin Choi, Seyeon Yoo, Yongsun Lee, Yongwoo Jo, Jeonghyun Lee, Younghyun Lim, Jaehyouk Choi
2018 — conf
A -242dB FOM and -75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC.
ISSCC
Taeho Seong, Yongsun Lee, Seyeon Yoo, Jaehyouk Choi
2018 — conf
A -31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection-locked frequency multipliers.
ISSCC
Heein Yoon, Juyeop Kim, Suneui Park, Younghyun Lim, Yongsun Lee, Jooeun Bang, Kyoohyun Lim, Jaehyouk Choi
2018 — conf
A 320µV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector.
ESSCIRC
Younghyun Lim, Jeonghyun Lee, Yongsun Lee, Seyeon Yoo, Jaehyouk Choi
2018 J jnl
A Low-Integrated-Phase-Noise 27-30-GHz Injection-Locked Frequency Multiplier With an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers.
IEEE J. Solid State Circuits
Seyeon Yoo, Seojin Choi, Juyeop Kim, Heein Yoon, Yongsun Lee, Jaehyouk Choi
2018 J jnl
A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique.
IEEE J. Solid State Circuits
Yongsun Lee, Taeho Seong, Seyeon Yoo, Jaehyouk Choi
2018 — conf
A switched-loop-filter PLL with fast phase-error correction technique.
ASP-DAC
Yongsun Lee, Taeho Seong, Seyeon Yoo, Jaehyouk Choi
2018 — conf
Injection-locked frequency multiplier with a continuous frequency-tracking loop for 5G transceivers.
ASP-DAC
Seyeon Yoo, Seojin Choi, Juyeop Kim, Heein Yoon, Yongsun Lee, Jaehyouk Choi
2017 — conf
19.2 A PVT-robust -39dBc 1kHz-to-100MHz integrated-phase-noise 29GHz injection-locked frequency multiplier with a 600µW frequency-tracking loop using the averages of phase deviations for mm-band 5G transceivers.
ISSCC
Seyeon Yoo, Seojin Choi, Juyeop Kim, Heein Yoon, Yongsun Lee, Jaehyouk Choi
2017 J jnl
An External Capacitor-Less Ultralow-Dropout Regulator Using a Loop-Gain Stabilizing Technique for High Power-Supply Rejection Over a Wide Range of Load Current.
IEEE Trans. Very Large Scale Integr. Syst.
Younghyun Lim, Jeonghyun Lee, Yongsun Lee, Seong-Sik Song, Hong-Teuk Kim, Ockgoo Lee, Jaehyouk Choi
2016 J jnl
A 0.56-2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2G-4G Multistandard Cellular Transceivers.
IEEE J. Solid State Circuits
Heein Yoon, Yongsun Lee, Younghyun Lim, Geum-Young Tak, Hong-Teuk Kim, Yo-Chuol Ho, Jaehyouk Choi
2016 — conf
A PVT-robust -59-dBc reference spur and 450-fsRMS jitter injection-locked clock multiplier using a voltage-domain period-calibrating loop.
VLSI Circuits
Yongsun Lee, Heein Yoon, Mina Kim, Jaehyouk Choi
2015 J jnl
A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier With a Two-Phase PVT-Calibrator for ΔΣ PLLs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yongsun Lee, Mina Kim, Taeho Seong, Jaehyouk Choi
2014 J jnl
A Wideband Dual-Mode LC-VCO With a Switchable Gate-Biased Active Core.
IEEE Trans. Circuits Syst. II Express Briefs
Heein Yoon, Yongsun Lee, Jae Joon Kim, Jaehyouk Choi
2014 J jnl
Ultralow In-Band Phase Noise Injection-Locked Frequency Multiplier Design Based on Open-Loop Frequency Calibration.
IEEE Trans. Circuits Syst. II Express Briefs
Taeho Seong, Yongsun Lee, Jaehyouk Choi