Yongsam Moon - RankMe

14 papers C 1Journal 10Unranked 3

Year	Rank	Type	Title / Venue / Authors
2016	J	`jnl`	Signal detector for 6-Gbps 55-nm CMOS Serial ATA receiver. IEICE Electron. Express Yongsam Moon
2012	J	`jnl`	Divide-by- IEICE Electron. Express Seon-Woo Hwang, Yongsam Moon
2010	J	`jnl`	A spread-spectrum clock generator for 6-Gbps Serial ATA transceiver. IEICE Electron. Express Yongsam Moon
2009	—	`conf`	1.2V 1.6Gb/s 56nm 6F ISSCC Yongsam Moon, Yong-Ho Cho, Hyun-Bae Lee, Byung-Hoon Jeong, Seok-Hun Hyun, Byungchul Kim, In-Chul Jeong, Seong-Young Seo, Junho Shin, Seok-Woo Choi, Ho-Sung Song, Jung-Hwan Choi, Kyehyun Kyung, Young-Hyun Jun, Kinam Kim
2009	J	`jnl`	TX rise/fall time control for multi-rate serial link. IEICE Electron. Express Yongsam Moon
2008	C	`conf`	Presetting pulse-based flip-flop. ISCAS Chul Soo Kim, Joo-Seong Kim, Bai-Sun Kong, Yongsam Moon, Young-Hyun Jun
2006	—	`conf`	A Quad 6Gb/s Multi-rate CMOS Transceiver with TX Rise/Fall-Time Control. ISSCC Yongsam Moon, Gijung Ahn, Hoon Choi, Namhoon Kim, Daeyun Shim
2005	J	`jnl`	A divide-by-16.5 circuit for 10-gb ethernet transceiver in 0.13-μm CMOS. IEEE J. Solid State Circuits Yongsam Moon, Sang-Hyun Lee, Daeyun Shim
2004	J	`jnl`	A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link. IEEE J. Solid State Circuits Yongsam Moon, Young-Soo Park, Namhoon Kim, Gijung Ahn, Hyun J. Shin, Deog-Kyoon Jeong
2002	J	`jnl`	A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit. IEEE J. Solid State Circuits Sang-Hyun Lee, Moon-Sang Hwang, Youngdon Choi, Sungjoon Kim, Yongsam Moon, Bong-Joon Lee, Deog-Kyoon Jeong, Wonchan Kim, Young-June Park, Gijung Ahn
2001	J	`jnl`	A 0.6-2.5-GBaud CMOS tracked 3 × oversampling transceiver with dead-zone phase detection for robust clock/data recovery. IEEE J. Solid State Circuits Yongsam Moon, Deog-Kyoon Jeong, Gijung Ahn
2000	J	`jnl`	An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance. IEEE J. Solid State Circuits Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog-Kyoon Jeong, Min-Kyu Kim
1999	—	`conf`	A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells. CICC Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog-Kyoon Jeong, Min-Kyu Kim
1997	J	`jnl`	A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL. IEEE J. Solid State Circuits Sungjoon Kim, Kyeongho Lee, Yongsam Moon, Deog-Kyoon Jeong, Yunho Choi, Hyung Kyu Lim