Yongqiang Lu

19 papers A* 1C 2Misc 2Journal 5Unranked 9
YearRankTypeTitle / Venue / Authors
2015 Misc conf
Mitigating Code-Reuse Attacks on CISC Architectures in a Hardware Approach.
SEC
Zhijiao Zhang, Ya-Shuai Lü, Yu Chen, Yongqiang Lu, Yuanchun Shi
2013 J jnl
A Scalable and Privacy-Aware Location-Sensing Model for Ephemeral Social Network Service.
Int. J. Distributed Sens. Networks
Yongqiang Lu, Dezhi Hong, Ying Wang, Yinghong Hou, Zhengwen Yang, Yu Chen, Yuanchun Shi, Alvin Chin
2013 Misc conf
Binding Hardware IPs to Specific FPGA Device via Inter-twining the PUF Response with the FSM of Sequential Circuits.
FCCM
Jiliang Zhang, Yaping Lin, Yongqiang Lu, Ray C. C. Cheung, Wenjie Che, Qiang Zhou, Jinian Bian
2012 J jnl
Efficient verification of IP watermarks in FPGA designs through lookup table content extracting.
IEICE Electron. Express
Jiliang Zhang, Yaping Lin, Wenjie Che, Qiang Wu, Yongqiang Lu, Kang Zhao
2012 — conf
Enhanced ALOHA Algorithm for Chirp Spread Spectrum Positioning.
ICPCA/SWS
Zhengwen Yang, Qiang Wu, Yongqiang Lu, Pei Lu, Yinghong Hou, Manman Peng
2012 J jnl
TimFastPlace: Critical-path based timing driven FastPlace.
IEICE Electron. Express
Jiliang Zhang, Yongqiang Lu, Qiang Zhou, Qiang Wu, Yaping Lin, Kang Zhao
2012 C conf
UE-based optimization for self-service community healthcare kiosk.
Healthcom
Wei Liu, Yongqiang Lu, Cai Chen, Yuanyuan Du, Fanxi Yan, Shuqi Xu
2011 — conf
A timing-perspective study on the wire model in placement.
ASICON
Liu Liu, Yongqiang Lu, Qiang Zhou
2010 C conf
A Low-Cost Ubiquitous Family Healthcare Framework.
UIC
Yongqiang Lu, Lei Zhang, Yu Chen, Yingjie Ren, Jing Liu, Weikang Yang, Yuanchun Shi
2010 — conf
A low power clock network placement framework.
ISQED
Dawei Liu, Qiang Zhou, Yongqiang Lu, Jinian Bian
2010 — conf
Useful clock skew optimization under a multi-corner multi-mode design framework.
ISQED
Weixiang Shen, Yici Cai, Wei Chen, Yongqiang Lu, Qiang Zhou, Jiang Hu
2008 — conf
An innovative Steiner tree based approach for polygon partitioning.
ASP-DAC
Yongqiang Lu, Qing Su, Jamil Kawa
2007 J jnl
An efficient quadratic placement based on search space traversing technology.
Integr.
Yongqiang Lu, Xianlong Hong, Qiang Zhou, Yici Cai, Jun Gu
2005 — conf
Clock network minimization methodology based on incremental placement.
ASP-DAC
Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu
2005 J jnl
Navigating Register Placement for Low Power Clock Network Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yongqiang Lu, Chin Ngai Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
2005 A* conf
Navigating registers in placement for clock network minimization.
DAC
Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
2005 — conf
Register placement for low power clock network.
ASP-DAC
Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
2004 — conf
Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration.
ISCAS (5)
Changqi Yang, Xianlong Hong, Hannah Honghua Yang, Qiang Zhou, Yici Cai, Yongqiang Lu
2003 — conf
Combining clustering and partitioning in quadratic placement.
ISCAS (4)
Yongqiang Lu, Xianlong Hong, Wenting Hou, Weimin Wu, Yici Cai