Yongliang Zhou

40 papers C 5Journal 26Unranked 9

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A Capacitor Discharge-Based SRAM CIM Macro Based on Hybrid-Domain for Convolutional Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. Bin Qiang, Yiming Wei, Yongliang Zhou, Xiulong Wu, Chunyu Peng
2026	J	`jnl`	Error-flagging assisted BCH decoder with compressed finite field traversal for STT-MRAM controllers. Microelectron. J. Yongliang Zhou, Xun Wu, Beibei Zhang, Weizhe Tan, Chunyu Peng, Xiulong Wu
2026	J	`jnl`	Low-temperature-drift voltage reference design using magnetic tunnel junctions. Integr. Yongliang Zhou, Yingxue Sun, Beibei Zhang, Wangyong Si, Jingxue Zhong, Weizhe Tan, Chunyu Peng, Xiulong Wu
2026	J	`jnl`	MTJ-back-gate SRAM CIM with replica quantization for temperature robust. Integr. Yongliang Zhou, Chengxing Dai, Yufei He, Xiulong Wu, Chunyu Peng
2025	J	`jnl`	A high charge-discharge stability SRAM 10T1C XOR CIM macro applied in BCAM and Hamming distance. Microelectron. J. Li Liu, Wei Hu, Zhen Yang, Yiming Wei, Chunyu Peng, Xiulong Wu, Zhiting Lin, Wenjuan Lu, Yongliang Zhou, Junning Chen
2025	J	`jnl`	Adaptive Temperature-Compensation of Charge-Pump PLL-Based MTJ/CMOS for Frequency Stability. IET Circuits Devices Syst. Chunyu Peng, Jingxue Zhong, Yingxue Sun, Weizhe Tan, Chengxing Dai, Xin Li, Xiulong Wu, Yongliang Zhou
2025	J	`jnl`	Dual-path synchronized discharge CIM architecture with bipolar computing unit for BWNs. Microelectron. J. Yongliang Zhou, Weizhe Tan, Zhen Yang, Chunyu Peng, Xiulong Wu
2025	J	`jnl`	Full-Array Boolean Logic CIM Macro With Self-Recycling 10T-SRAM Cell for AES Systems. IEEE Trans. Very Large Scale Integr. Syst. Xin Li, Ying Pan, Qian Jin, Lintao Chen, Yang Lou, Baofa Wu, Jiajun Long, Yongliang Zhou, Chunyu Peng, Xiulong Wu, Zhiting Lin
2025	C	`conf`	MTJ based Temperature-Adaptive VCO (TAVCO) for Compensating CP-PLL Frequency Drift. ISCAS Yongliang Zhou, Jingxue Zhong, Yingxue Sun, Chengxing Dai, Weizhe Tan, Chunyu Peng, Wenjuan Lu, Xin Li, Zhiting Lin, Xiulong Wu
2025	C	`conf`	MTJ based temperature compensated beta multiplier Voltage Reference. ISCAS Yongliang Zhou, Yingxue Sun, Jingxue Zhong, Chengxing Dai, Weizhe Tan, Chunyu Peng, Xin Li, Zhigang Li, Zhiting Lin, Xiulong Wu
2024	J	`jnl`	A CFMB STT-MRAM-Based Computing-in-Memory Proposal With Cascade Computing Unit for Edge AI Devices. IEEE Trans. Circuits Syst. I Regul. Pap. Yongliang Zhou, Zixuan Zhou, Yiming Wei, Zhen Yang, Xiao Lin, Chenghu Dai, Licai Hao, Chunyu Peng, Hao Cai, Xiulong Wu
2024	C	`conf`	A Timing-Shared Adaptive Sensing Methodology for Low-Voltage SRAM. ISCAS Yongliang Zhou, Zhen Yang, Yiming Wei, Xiao Lin, Saiai Wu, Wenjuan Lu, Chunyu Peng, Xin Li, Xiulong Wu
2024	J	`jnl`	An 8b-Precison 16-Kb FDSOI 8T SRAM CIM macro based on time-domain for energy-efficient edge AI devices. Microelectron. J. Yongliang Zhou, Yiming Wei, Tianzhu Xiong, Zixuan Zhou, Zhen Yang, Xiao Lin, Wei Hu, Xiulong Wu, Chunyu Peng
2024	J	`jnl`	Configurable in-memory computing architecture based on dual-port SRAM. Microelectron. J. Yue Zhao, Yunlong Liu, Jian Zheng, Zhongzhen Tong, Xin Wang, Runru Yu, Xiulong Wu, Yongliang Zhou, Chunyu Peng, Wenjuan Lu, Qiang Zhao, Zhiting Lin
2024	J	`jnl`	Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design. IEEE Trans. Very Large Scale Integr. Syst. Licai Hao, Yaling Wang, Yunlong Liu, Shiyu Zhao, Xinyi Zhang, Yang Li, Wenjuan Lu, Chunyu Peng, Qiang Zhao, Yongliang Zhou, Chenghu Dai, Zhiting Lin, Xiulong Wu
2024	J	`jnl`	Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies. IEEE Trans. Very Large Scale Integr. Syst. Licai Hao, Xinyi Zhang, Chenghu Dai, Qiang Zhao, Wenjuan Lu, Chunyu Peng, Yongliang Zhou, Zhiting Lin, Xiulong Wu
2024	J	`jnl`	Timing Optimization Model and PVT Tracked Scheme for STT-MRAM Voltage-Mode Sense. IEEE Trans. Circuits Syst. I Regul. Pap. Yongliang Zhou, Xiao Lin, Zixuan Zhou, Yingxue Sun, Yiming Wei, Zhen Yang, Chengxing Dai, Jingxue Zhong, Xiulong Wu, Chunyu Peng
2024	J	`jnl`	Ultra8T: A sub-threshold 8T SRAM with leakage detection. Integr. Shan Shen, Hao Xu, Yongliang Zhou, Ming Ling, Wenjian Yu
2023	—	`conf`	A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference. ISSCC Hao Cai, Zhongjian Bian, Yaoru Hou, Yongliang Zhou, Jia-Le Cui, Yanan Guo, Xiaoyun Tian, Bo Liu, Xin Si, Zhen Wang, Jun Yang, Weiwei Shan
2023	—	`conf`	A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs. ISSCC An Guo, Xin Si, Xi Chen, Fangyuan Dong, Xingyu Pu, Dongqi Li, Yongliang Zhou, Lizheng Ren, Yeyang Xue, Xueshan Dong, Hui Gao, Yiran Zhang, Jingmin Zhang, Yuyao Kong, Tianzhu Xiong, Bo Wang, Hao Cai, Weiwei Shan, Jun Yang
2023	—	`conf`	A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks. ISSCC Bo Wang, Chen Xue, Zhongyuan Feng, Zhaoyang Zhang, Han Liu, Lizheng Ren, Xiang Li, Anran Yin, Tianzhu Xiong, Yeyang Xue, Shengnan He, Yuyao Kong, Yongliang Zhou, An Guo, Xin Si, Jun Yang
2023	J	`jnl`	A Single-Ended Offset-Canceling Sense Amplifier Enabling Wide-Voltage Operations. IEEE Trans. Circuits Syst. II Express Briefs Shan Shen, Hao Xu, Yongliang Zhou, Wenjian Yu
2023	J	`jnl`	Ultra8T: A Sub-Threshold 8T SRAM with Leakage Detection. CoRR Shan Shen, Hao Xu, Yongliang Zhou, Ming Ling, Wenjian Yu
2022	—	`conf`	A 22-nm FDSOI 8T SRAM Based Time-Domain CIM for Energy-Efficient DNN Accelerators. APCCAS Yongliang Zhou, Zuo Cheng, Han Liu, Tianzhu Xiong, Bo Wang
2022	C	`conf`	SNNIM: A 10T-SRAM based Spiking-Neural-Network-In-Memory architecture with capacitance computation. ISCAS Bo Wang, Chen Xue, Han Liu, Xiang Li, Anran Yin, Zhongyuan Feng, Yuyao Kong, Tianzhu Xiong, Haiming Hsu, Yongliang Zhou, An Guo, Yufei Wang, Jun Yang, Xin Si
2022	C	`conf`	ShareFloat CIM: A Compute-In-Memory Architecture with Floating-Point Multiply-and-Accumulate Operations. ISCAS An Guo, Yongliang Zhou, Bo Wang, Tianzhu Xiong, Chen Xue, Yufei Wang, Xin Si, Jun Yang
2022	J	`jnl`	Writing-only in-MRAM computing paradigm for ultra-low power applications. Microprocess. Microsystems Bo Liu, Mingyue Liu, Yongliang Zhou, Xiaofeng Hong, Hao Cai, Lirida Alves de Barros Naviner
2021	J	`jnl`	A survey of in-spin transfer torque MRAM computing. Sci. China Inf. Sci. Hao Cai, Bo Liu, Juntong Chen, Lirida A. B. Naviner, Yongliang Zhou, Zhen Wang, Jun Yang
2021	—	`conf`	Challenge and Trend of SRAM Based Computation-in-Memory Circuits for AI Edge Devices. ASICON Xin Si, Yongliang Zhou, Jun Yang, Meng-Fan Chang
2021	—	`conf`	Design Challenges and Methodology of High-Performance SRAM-Based Compute-in-Memory for AI Edge Devices. UCET Yufei Wang, Yongliang Zhou, Bo Wang, Tianzhu Xiong, Yuyao Kong, Xin Si
2021	—	`conf`	Design Methodology towards High-Precision SRAM based Computation-in-Memory for AI Edge Devices. ISOCC Tianzhu Xiong, Yongliang Zhou, Yuyao Kong, Bo Wang, An Guo, Yufei Wang, Chen Xue, Haiming Hsu, Xin Si, Jun Yang
2021	J	`jnl`	Toward Energy-Efficient STT-MRAM Design With Multi-Modes Reconfiguration. IEEE Trans. Circuits Syst. II Express Briefs Hao Cai, Juntong Chen, Yongliang Zhou, Weisheng Zhao
2020	J	`jnl`	A Self-Timed Voltage-Mode Sensing Scheme With Successive Sensing and Checking for STT-MRAM. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. Yongliang Zhou, Hao Cai, Lei Xie, Menglin Han, Mingyue Liu, Shi Xu, Bo Liu, Weisheng Zhao, Jun Yang
2020	J	`jnl`	Interplay Bitwise Operation in Emerging MRAM for Efficient In-memory Computing. CCF Trans. High Perform. Comput. Hao Cai, Honglan Jiang, Yongliang Zhou, Menglin Han, Bo Liu
2020	J	`jnl`	MTJ-LRB: Proposal of MTJ-Based Loop Replica Bitline as MRAM Device-Circuit Interaction for PVT-Robust Sensing. IEEE Trans. Circuits Syst. Yongliang Zhou, Hao Cai, Bo Liu, Weisheng Zhao, Jun Yang
2020	J	`jnl`	Magnetic Tunnel Junction Applications. Sensors Nilson Maciel, Elaine Crespo Marques, Lirida A. B. Naviner, Yongliang Zhou, Hao Cai
2019	—	`conf`	A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement. NANOARCH Yongliang Zhou, Menglin Han, Mingyue Liu, Hao Cai, Bo Liu, Jun Yang
2016	J	`jnl`	Robust activating timing for SRAM SA with replica cell voltage boosted circuit. IEICE Electron. Express Zhengping Li, Mingming Xie, Xincun Ji, Yongliang Zhou
2011	J	`jnl`	Rank-two residue iteration method for nonnegative matrix factorization. Neurocomputing Hongwei Liu, Yongliang Zhou
2010	—	`conf`	Analysis of how to use the GEB developing. ICEE Na Wei, Yongliang Zhou