Yongchan Ban

11 papers A* 4A 3Journal 2Unranked 2
YearRankTypeTitle / Venue / Authors
2015 — conf
Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line.
ACM Great Lakes Symposium on VLSI
Wei Ye, Bei Yu, David Z. Pan, Yongchan Ban, Lars Liebmann
2012 A conf
Dealing with IC manufacturability in extreme scaling (Embedded tutorial paper).
ICCAD
Bei Yu, Jhih-Rong Gao, Duo Ding, Yongchan Ban, Jae-Seok Yang, Kun Yuan, Minsik Cho, David Z. Pan
2011 A conf
Doppler: DPL-aware and OPC-friendly gridless detailed routing with mask density balancing.
ICCAD
Yen-Hung Lin, Yongchan Ban, David Z. Pan, Yih-Lang Li
2011 A* conf
Flexible 2D layout decomposition framework for spacer-type double pattering lithography.
DAC
Yongchan Ban, Kevin Lucas, David Z. Pan
2011 A* conf
Layout aware line-edge roughness modeling and poly optimization for leakage minimization.
DAC
Yongchan Ban, Jae-Seok Yang
2011 J jnl
Modeling of Layout Aware Line-Edge Roughness and Poly Optimization for Leakage Minimization.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Yongchan Ban, David Z. Pan
2010 A* conf
Compact modeling and robust layout optimization for contacts in deep sub-wavelength lithography.
DAC
Yongchan Ban, David Z. Pan
2010 — conf
Total sensitivity based dfm optimization of standard library cells.
ISPD
Yongchan Ban, Savithri Sundareswaran, David Z. Pan
2009 J jnl
ELIAD: Efficient Lithography Aware Detailed Routing Algorithm With Compact and Macro Post-OPC Printability Prediction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan
2008 A conf
Double patterning technology friendly detailed routing.
ICCAD
Minsik Cho, Yongchan Ban, David Z. Pan
2008 A* conf
ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction.
DAC
Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan