| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2024 | J | jnl |
ERA-BS: Boosting the Efficiency of ReRAM-Based PIM Accelerator With Fine-Grained Bit-Level Sparsity.
IEEE Trans. Computers
|
| 2024 | J | jnl |
IEEE Trans. Parallel Distributed Syst.
|
| 2023 | J | jnl |
IEEE Trans. Intell. Transp. Syst.
|
| 2023 | A* | conf |
DAC
|
| 2023 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2022 | J | jnl |
J. Syst. Archit.
|
| 2022 | Misc | conf |
ICASSP
|
| 2022 | A* | conf |
DAC
|
| 2022 | A* | conf |
DAC
|
| 2022 | C | conf |
ICCD
|
| 2022 | A* | conf |
DAC
|
| 2022 | A* | conf |
AAAI
|
| 2022 | B | conf |
ICMR
|
| 2022 | B | conf |
ICMR
|
| 2021 | A | conf |
Bit-Transformer: Transforming Bit-level Sparsity into Higher Preformance in ReRAM-based Accelerator.
ICCAD
|
| 2021 | J | jnl |
CoRR
|
| 2021 | A | conf |
ICME
|
| 2021 | C | conf |
VCIP
|
| 2021 | J | jnl |
CoRR
|
| 2021 | J | jnl |
CoRR
|
| 2020 | B | conf |
ICMR
|