Yong Liu

20 papers Journal 8Unranked 12
YearRankTypeTitle / Venue / Authors
2016 — conf
3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI.
ISSCC
Sergey V. Rylov, Troy J. Beukema, Zeynep Toprak Deniz, Thomas Toifl, Yong Liu, Ankur Agrawal, Peter Buchmann, Alexander V. Rylyakov, Michael P. Beakes, Benjamin D. Parker, Mounir Meghelli
2016 J jnl
A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration.
IEEE J. Solid State Circuits
Timothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Michael P. Beakes, Mounir Meghelli, Daniel J. Friedman
2015 J jnl
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.
IEEE J. Solid State Circuits
Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman
2015 — conf
A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration.
CICC
Timothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Mounir Meghelli, Daniel J. Friedman
2014 — conf
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology.
CICC
Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman
2013 — conf
A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI.
ISSCC
Yong Liu, Ping-Hsuan Hsieh, Seongwon Kim, Jae-sun Seo, Robert K. Montoye, Leland Chang, José A. Tierno, Daniel J. Friedman
2012 J jnl
A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS.
IEEE J. Solid State Circuits
Ankur Agrawal, John F. Bulzacchelli, Timothy O. Dickson, Yong Liu, José A. Tierno, Daniel J. Friedman
2012 — conf
A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS.
ISSCC
Ankur Agrawal, John F. Bulzacchelli, Timothy O. Dickson, Yong Liu, José A. Tierno, Daniel J. Friedman
2012 — conf
A compact low-power 3D I/O in 45nm CMOS.
ISSCC
Yong Liu, Wing K. Luk, Daniel J. Friedman
2012 J jnl
An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects.
IEEE J. Solid State Circuits
Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Bing Dang, Cornelia K. Tsang, Paul S. Andry, John F. Bulzacchelli, Herschel A. Ainspan, Xiaoxiong Gu, Lavanya Turlapati, Michael P. Beakes, Benjamin D. Parker, John U. Knickerbocker, Daniel J. Friedman
2012 — conf
Solid-state and biological systems interface.
ESSCIRC
Nan Sun, Yong Liu, Ling Qin, Guangyu Xu, Donhee Ham
2011 — conf
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons.
CICC
Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D. Parker, Steven K. Esser, Robert K. Montoye, Bipin Rajendran, José A. Tierno, Leland Chang, Dharmendra S. Modha, Daniel J. Friedman
2009 J jnl
A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS.
IEEE J. Solid State Circuits
Byungsub Kim, Yong Liu, Timothy O. Dickson, John F. Bulzacchelli, Daniel J. Friedman
2009 — conf
A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS.
ISSCC
Yong Liu, Byungsub Kim, Timothy O. Dickson, John F. Bulzacchelli, Daniel J. Friedman
2009 J jnl
CMOS RF Biosensor Utilizing Nuclear Magnetic Resonance.
IEEE J. Solid State Circuits
Nan Sun, Yong Liu, Hakho Lee, Ralph Weissleder, Donhee Ham
2008 — conf
CMOS Mini Nuclear Magnetic Resonance System and its Application for Biomolecular Sensing.
ISSCC
Yong Liu, Nan Sun, Hakho Lee, Ralph Weissleder, Donhee Ham
2008 J jnl
Fast-Lock Hybrid PLL Combining Fractional-N and Integer-N Modes of Differing Bandwidths.
IEEE J. Solid State Circuits
Kyoungho Woo, Yong Liu, Eunsoo Nam, Donhee Ham
2007 — conf
All-Digital Dynamic Self-Detection and Self-Compensation of Static Phase Offsets in Charge-Pump PLLs.
ISSCC
Yong Liu, Woogeun Rhee, Daniel J. Friedman, Donhee Ham
2006 J jnl
IC/microfluidic hybrid system for magnetic manipulation of biological cells.
IEEE J. Solid State Circuits
Hakho Lee, Yong Liu, Robert M. Westervelt, Donhee Ham
2002 — conf
A Flexible Embedded SRAM Compiler.
DELTA
Yong Liu, Zhiqiang Gao, Xiangqing He