Yong Lim

27 papers C 1Journal 9Unranked 16
YearRankTypeTitle / Venue / Authors
2026 — conf
A PVT Variation- and Attack-Tolerant Metastability-Based TRNG Using Binary Search in 2nm.
ISSCC
Yelim Youn, Yong Lim, Jongmi Lee, Dongyeon Hong, Wan Kim, Yong-Sik Kwak, Kyoung-Jun Moon, Bogyeong Kang, Sangmin Yoo
2025 J jnl
An Intrinsically Linear Multi-Rate Continuous-Time Zoom ADC Achieving 97.4-dB DR and 105.7-dB SFDR in 50-kHz Signal Bandwidth.
IEEE J. Solid State Circuits
Junghyun Yoon, Moon Hyung Jang, Changuk Lee, Yong Lim, Youngcheol Chae
2024 — conf
9.2 A 2.08mW 64.4dB SNDR 400MS/s 12b Pipelined-SAR ADC using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8nm.
ISSCC
Yong Lim, Jaehoon Lee, Jongmi Lee, Kwangmin Lim, Seunghyun Oh, Jongwoo Lee, Sung-Ung Kwak
2024 — conf
9.6 A 6
ISSCC
Jongmi Lee, Seong-Eun Cho, Jaehoon Lee, Yong Lim, Seunghyun Oh, Jongwoo Lee, Sung-Ung Kwak
2024 J jnl
A 2.08-mW 64.4-dB SNDR 400-MS/s Pipelined- SAR ADC Using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8 nm.
IEEE J. Solid State Circuits
Yong Lim, Jaehoon Lee, Jongmi Lee, Kwangmin Lim, Seunghyun Oh, Jongwoo Lee
2024 — conf
A 2.8-to-7.2GT/s DDR5 Registering Clock Driver IC with Parallel-Data Timing and Pin-to-Pin Skew Calibration for a Dual In-Line Memory Module.
A-SSCC
Joomyoung Kim, Jaehong Jung, Kwangmin Lim, Barosaim Sung, Jaekwon Kim, Baekmin Lim, Tae-Gun Noh, Jaehoon Lee, Hyun-Gi Seok, Youngsea Cho, Gyusik Kim, Takahiro Nomiyama, Sunhye Kang, Yeongcheol Jeong, Sanguk Cho, Gyumin Kim, Do-Hyun Oh, JaeNam Kim, Yong Lim, Seungjin Kim, Seunghyun Oh, Jongwoo Lee
2024 J jnl
A Fully Integrated, Low-Noise, Cost-Effective Single-Crystal-Oscillator-Based Clock Management IC in 28-nm CMOS.
IEEE J. Solid State Circuits
Jaehong Jung, Seunghyun Oh, Joomyoung Kim, Jinhyeon Lee, Wonkang Kim, Euiyoung Park, Seungyong Bae, Seungjin Kim, Jaehoon Lee, Yelim Youn, Yeongcheol Jeong, Sungsik Park, Kyungsoo Lee, Yong Lim, Junho Huh, Jongwoo Lee
2023 — conf
A 243μW 97.4dB-DR 50kHz-BW Multi-Rate CT Zoom ADC with Inherent DAC Mismatch Tolerance.
CICC
Junghyun Yoon, Moon Hyung Jang, Changuk Lee, Yong Lim, Youngcheol Chae
2023 J jnl
SQuARe: A Large-Scale Dataset of Sensitive Questions and Acceptable Responses Created Through Human-Machine Collaboration.
CoRR
Hwaran Lee, Seokhee Hong, Joonsuk Park, Takyoung Kim, Meeyoung Cha, Yejin Choi, Byoung Pil Kim, Gunhee Kim, Eun-Ju Lee, Yong Lim, Alice Oh, Sangchul Park, Jung-Woo Ha
2023 — conf
SQuARe: A Large-Scale Dataset of Sensitive Questions and Acceptable Responses Created through Human-Machine Collaboration.
ACL (1)
Hwaran Lee, Seokhee Hong, Joonsuk Park, Takyoung Kim, Meeyoung Cha, Yejin Choi, Byoung Pil Kim, Gunhee Kim, Eun-Ju Lee, Yong Lim, Alice Oh, Sangchul Park, Jung-Woo Ha
2022 — conf
A 0.56mW 63.6dB SNDR 250MS/s SAR ADC in 8nm FinFET.
VLSI Technology and Circuits
Jaehoon Lee, Yong Lim, Jongmi Lee, Taejin Jang, Kwonwoo Kang, Jongpil Cho, Seunghyun Oh, Jongwoo Lee
2022 — conf
A Pipeline ADC with Negative C-assisted SC Amplifier Canceling Gain Error and Nonlinearity.
ESSCIRC
Woojin Jang, Gyeong-Gu Kang, Yong Lim, Hyun-Sik Kim
2022 J jnl
A Single Path Digital-IF Receiver Supporting Inter/Intra 5-CA With a Single Integer LO-PLL in 14-nm CMOS FinFET.
IEEE J. Solid State Circuits
Barosaim Sung, Hyun-Gi Seok, Jaekwon Kim, Jaehoon Lee, Taejin Jang, Ilhoon Jang, Youngmin Kim, Anna Yu, Jong-Hyun Jang, Jiyoung Lee, Jeongyeol Bae, Euiyoung Park, Sung-Jun Lee, Seokwon Lee, Joohan Kim, Beomkon Kim, Yong Lim, Seunghyun Oh, Jongwoo Lee
2022 — conf
A Single-Crystal-Oscillator-Based Clock-Management IC with 18× Start-Up Time Reduction and 0.68ppm/ºC Duty-Cycled Machine-Learning-Based RCO Calibration.
ISSCC
Jaehong Jung, Seunghyun Oh, Joo-Myoung Kim, Gihyeok Ha, Jinhyeon Lee, Seungjin Kim, Euiyoung Park, Jaehoon Lee, Yelim Yoon, Seungyong Bae, Wonkang Kim, Yong Lim, Kyungsoo Lee, Junho Huh, Jongwoo Lee, Thomas Byunghak Cho
2022 — conf
A Single-Path Digital-IF Receiver Supporting Inter/Intra 5-CA with a Single Integer LO-PLL in 14nm CMOS FinFET.
ISSCC
Barosaim Sung, Hyun-Gi Seok, Jaekwon Kim, Jaehoon Lee, Taejin Jang, Ilhoon Jang, Youngmin Kim, Anna Yu, Jong-Hyun Jang, Jiyoung Lee, Jeongyeol Bae, Euiyoung Park, Sung-Jun Lee, Seokwon Lee, Joohan Kim, Beomkon Kim, Yong Lim, Seunghyun Oh, Jongwoo Lee, Thomas Byunghak Cho, Inyup Kang
2022 — ch.
Data Governance and Trust: Lessons from South Korean Experiences Coping with COVID-19.
The Cambridge Handbook of Responsible Artificial Intelligence
Sangchul Park, Yong Lim, Haksoo Ko
2021 — conf
10.1 A 116μ W 104.4dB-DR 100.6dB-SNDR CT Δ∑ Audio ADC Using Tri-Level Current-Steering DAC with Gate-Leakage Compensated Off-Transistor-Based Bias Noise Filter.
ISSCC
Chilun Lo, Jongmi Lee, Yong Lim, Younghyun Yoon, Hyunseok Hwang, Jaehoon Lee, Moo-Yeol Choi, Myungjin Lee, Seunghyun Oh, Jongwoo Lee
2020 C conf
An Effective Transconductance Controlled Offset Calibration for Dynamic Comparators.
ISCAS
Jaehoon Lee, Yong Lim, Barosaim Sung, Seunghyun Oh, Jung-Hoon Chun, Jongwoo Lee
2019 — conf
A Blocker-Tolerant Direct Sampling Receiver for Wireless Multi-Channel Communication in 14nm FinFET CMOS.
A-SSCC
Barosaim Sung, Chilun Lo, Jaehoon Lee, Sangdon Jung, Seungjin Kim, Jaehong Jung, Seungyong Bae, Youngsea Cho, Yong Lim, Dooseok Choi, Myeongcheol Shin, Soonwoo Choi, Byungki Han, Seunghyun Oh, Jongwoo Lee
2017 J jnl
A 1.5-GHz 6.144T Correlations/s 64 × 64 Cross-Correlator With 128 Integrated ADCs for Real-Time Synthetic Aperture Imaging.
IEEE J. Solid State Circuits
John Bell, Phil Knag, Shuanghong Sun, Yong Lim, Thomas Chen, Jeffrey Fredenburg, Chia-Hsiang Chen, Chunyang Zhai, Aaron Z. Rocca, Nicholas Collins, Andres Tamez, Jorge Pernillo, Justin M. Correll, Alan B. Tanner, Zhengya Zhang, Michael P. Flynn
2016 — conf
A 16-channel noise-shaping machine learning analog-digital interface.
VLSI Circuits
Fred N. Buhler, Adam E. Mendrela, Yong Lim, Jeffrey A. Fredenburg, Michael P. Flynn
2015 — conf
26.1 A 1mW 71.5dB SNDR 50MS/S 13b fully differential ring-amplifier-based SAR-assisted pipeline ADC.
ISSCC
Yong Lim, Michael P. Flynn
2015 J jnl
A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC.
IEEE J. Solid State Circuits
Yong Lim, Michael P. Flynn
2015 J jnl
A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers.
IEEE J. Solid State Circuits
Yong Lim, Michael P. Flynn
2014 — conf
11.5 A 100MS/s 10.5b 2.46mW comparator-less pipeline ADC using self-biased ring amplifiers.
ISSCC
Yong Lim, Michael P. Flynn
2010 — conf
A 1.1e- temporal noise 1/3.2-inch 8Mpixel CMOS image sensor using pseudo-multiple sampling.
ISSCC
Yong Lim, Kyoungmin Koh, Kyungmin Kim, Han Yang, Juha Kim, Youngkyun Jeong, Seungjin Lee, Hansoo Lee, Sin-Hwan Lim, Yunseok Han, Jinwoo Kim, Jaecheol Yun, Seogheon Ham, Yun-Tae Lee
1985 J jnl
An interpolation technique for computing the DFT of a sparse sequence.
IEEE Trans. Acoust. Speech Signal Process.
Yong Lim