Yong Chen - RankMe

136 papers C 4Journal 91Unranked 41

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	25.10 A 65nm 0.066pJ/b Floating-Latch-Based True Random Number Generator Resilient to Power-Noise Injection Attacks. ISSCC Kai Cheng, Yunbo Huang, Zunsong Yang, Li Wang, Hongyu Ren, Xiaoyu Shan, Pui-In Mak, Yong Chen, Bo Li
2026	J	`jnl`	A 10-Bit 2-GS/s Voltage-Time-Pipelined Hybrid ADC with One-Hot Background Calibration Scoring > 60-dB SFDR in 28-nm CMOS. Circuits Syst. Signal Process. Yuan Chang, Chenghao Zhang, Yihang Yang, Maliang Liu, Yintang Yang, Yong Chen
2026	J	`jnl`	A 19.4-fs IEEE J. Solid State Circuits Jinhai Xiao, Yong Chen, Ningyi Zhang, Xiaolong Liu, Rui Liu, Junao Zhu, Chenghao Zhang, Peng Luo, Maliang Liu, Yintang Yang, Xiaohua Ma, Yue Hao
2026	J	`jnl`	A 28-nm 88.3-TFLOPS/W POSIT-Approximate-Calculation-Based Digital Computing-in-Memory Macro Incorporating Final-Cycle Fusion and Joint Skipping. IEEE J. Solid State Circuits Hao Wu, Yong Chen, Ming Li, Bingxin Zhang, Rui Zhang, Yiyang Yuan, Yiming Yang, Jinshan Yue, Xinghua Wang, Xiaoran Li, Feng Zhang
2026	J	`jnl`	A 40-GS/s 8-bit Time-Interleaved ADC Featuring SFDR-Enhanced Sampling and Power-Efficient Time-Domain Quantization in 28-nm CMOS. IEEE J. Solid State Circuits Chenghao Zhang, Maliang Liu, Yuan Chang, Yihang Yang, Jinhai Xiao, Yintang Yang, Yong Chen
2026	J	`jnl`	Capacitive Cold Start-Up Charge Pump Mechanism and Challenges: A Review. IEEE Access Khang Yian Ng, Harikrishnan Ramiah, Tian Siang Ho, Yi Chen Lee, Teck Seong Chang, En Hao Lee, Tan Yee Chyan, Yong Chen
2026	J	`jnl`	Comprehensive Overview and Mitigation Strategies of Nonlinear Transistor Behavior in CMOS Ambient RF Energy Harvesting Systems. IEEE Access Jamie How Peng Yong, Harikrishnan Ramiah, Yi Chen Lee, Wen Xun Lian, Kishore Kumar Pakkirisami Churchill, Yong Chen
2025	—	`conf`	A 0.16mm CICC Heyang Zhao, Yuxuan He, Yunsong Tao, Zhishuai Zhang, Yong Chen, Yi Zhong, Lu Jie, Nan Sun
2025	—	`conf`	A 22.4-25.6GHz Ping-Pong Sub-Sampling PLL Featuring Unified Supply Voltage and Balanced 2 CICC Yunbo Huang, Zunsong Yang, Hongyu Ren, Rui Paulo Martins, Yan Lu, Nan Sun, Nan Qi, Yong Chen
2025	J	`jnl`	A 28-nm 19.9-to-258.5-TOPS/W 8b Digital Computing-in-Memory Processor With Two-Cycle Macro Featuring Winograd-Domain Convolution and Macro-Level Parallel Dual-Side Sparsity. IEEE J. Solid State Circuits Hao Wu, Yong Chen, Yiyang Yuan, Jinshan Yue, Xinghua Wang, Xiaoran Li, Feng Zhang
2025	J	`jnl`	A 28-nm 8-Bit 16-GS/ DAC With >60 dBc/>40 dBc SFDR Up To 2.3 GHz/5.4 GHz Using 4-Channel NRZ-Output-Overlapped Time-Interleaving. IEEE Trans. Circuits Syst. II Express Briefs Sihao Chen, Chengyu Huang, Limeng Sun, Yang Liu, Wenjun Tang, Jiaxuan Fan, Nan Sun, Yong Chen, Huazhong Yang, Xueqing Li
2025	J	`jnl`	A 56-Gb/s, 6.3-pJ/bit PAM-4 DFB Laser Driver Incorporating Asymmetric Equalization and Integrated CDR in 28 nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Yang Min, Nan Qi, Yihan Chen, Yi Zhang, Minye Zhu, Guike Li, Yonghui Lin, Huiyao Peng, Mo Guang, Kaiwen Long, Zhao Zhang, Jian Liu, Nanjian Wu, Jingbo Shi, Yong Chen, Frank F. Shi, Liyuan Liu
2025	J	`jnl`	A Capacitorless Flipped-Voltage-Follower-Based Low-Dropout Regulator Incorporating Adaptive-Compensation Buffer. IEEE Trans. Very Large Scale Integr. Syst. Tan Yee Chyan, Harikrishnan Ramiah, Sharifah Wan Muhamad Hatta, Chee-Cheow Lim, Rui Paulo Martins, Pui-In Mak, Yong Chen
2025	J	`jnl`	A General-Purpose Computing Core With Cooperative Motion Detection and Feature Extraction for Always-On PWM Image Sensors. IEEE Trans. Very Large Scale Integr. Syst. Jinyu Gao, Ye Zhao, Ziyuan Wang, Long Chen, Aoming Zhan, Qihang Jiang, Feng Zhang, Yong Chen, Shushan Qiao
2025	J	`jnl`	A Harmonic-Suppressed GaN Power Amplifier Using Artificial Coupled Resonator. IEEE Trans. Very Large Scale Integr. Syst. Letian Guo, Jincheng Zhang, Lihe Nie, Jian Wang, Yong Chen, Junyan Ren, Shunli Ma
2025	J	`jnl`	A Minimal Loss Gate-Biasing Technique for CMOS Rectifier Achieving 22-dB PDR in GSM900 Ambient RFEH Applications. IEEE Trans. Circuits Syst. II Express Briefs Yi Chen Lee, Harikrishnan Ramiah, Tian Siang Ho, Fu Qi Chua, Wen Xun Lian, Kishore Kumar Pakkirisami Churchill, Yong Chen
2025	J	`jnl`	A Quad-Core VCO Incorporating Area-Saving Folded S-Shaped Tail Filtering in 28-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Shan Lu, DanYu Wu, Xuan Guo, Hanbo Jia, Yong Chen, Xinyu Liu
2025	J	`jnl`	A Switch-as-Resistor Self-Adaptive Gate-Biasing Technique for Optimized Forward and Reverse Conduction in a CMOS Rectifier. IEEE Trans. Circuits Syst. II Express Briefs Yi Chen Lee, Harikrishnan Ramiah, Tian Siang Ho, Fu Qi Chua, Wen Xun Lian, Kishore Kumar Pakkirisami Churchill, Yong Chen
2025	J	`jnl`	An 8-Bit 4-GS/s Single-Channel Two-Step ADC Featuring Non-Symmetrical Pipeline Timing and Hybrid-Loop Amplifier. IEEE Trans. Very Large Scale Integr. Syst. Chenghao Zhang, Maliang Liu, Yuan Chang, Yihang Yang, Jinhai Xiao, Yintang Yang, Yuanjin Zheng, Yong Chen
2025	J	`jnl`	Area-efficient ultra-wide-tuning-range ring oscillators in 65-nm complementary metal-oxide-semiconductor. Int. J. Circuit Theory Appl. Chaowei Yang, Yong Chen, Kai Cheng, Paolo Stefano Crovetti, Rui Paulo Martins, Pui-In Mak
2025	J	`jnl`	Evolution of and Perspectives on Differential-Pair-Based CMOS Variable Gain Amplifiers With Linear-in-Decibel Gain Control: A Tutorial. Int. J. Circuit Theory Appl. Siqi Wang, Zhenghao Lu, Zhong Tang, Xiaopeng Yu, Hanming Wu, Kiat Seng Yeo, Yong Chen
2025	J	`jnl`	Relaxation Digital-to-Analog Converters Featuring Self-Calibration and Parasitics-Induced Error Suppression in 180-nm CMOS. IEEE Access Roberto Rubino, Francesco Musolino, Pedro Toledo, Yong Chen, Anna Richelli, Paolo Stefano Crovetti
2025	J	`jnl`	Review and Perspective on Reverse Leakage Current Mitigation for Extended PDR in Fully Integrated RF Energy Harvesting System. IEEE Access Yan Joe Cheong, Harikrishnan Ramiah, Wen Xun Lian, Yi Chen Lee, Kishore Kumar Pakkirisami Churchill, Yong Chen
2025	J	`jnl`	Ultra-Low-V IEEE Trans. Circuits Syst. I Regul. Pap. Tian Siang Ho, Harikrishnan Ramiah, Kishore Kumar Pakkirisami Churchill, Andrea Ballo, Wen Xun Lian, Yi Chen Lee, Yong Chen
2024	—	`conf`	7.4 A 0.027mm ISSCC Yunbo Huang, Yong Chen, Zunsong Yang, Rui Paulo Martins, Pui-In Mak
2024	—	`conf`	A 0.0006-mm A-SSCC Zhicheng Dong, Xiaoteng Zhao, Zekai Yang, Xianting Su, Haolin Han, Feng Bu, Rong Zhou, Depeng Sun, Yong Chen, Shubin Liu, Ruixue Ding, Zhangming Zhu
2024	J	`jnl`	A 0.012-mm Int. J. Circuit Theory Appl. Kai Cheng, Yong Chen, Paolo Stefano Crovetti, Rui Paulo Martins, Pui-In Mak
2024	—	`conf`	A 0.144 mm CICC Xinyu Shen, Zhao Zhang, Yong Chen, Yixi Li, Yidan Zhang, Guike Li, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu
2024	J	`jnl`	A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity. IEEE Trans. Circuits Syst. I Regul. Pap. Hao Wu, Yong Chen, Yiyang Yuan, Jinshan Yue, Xiangqu Fu, Qirui Ren, Qing Luo, Pui-In Mak, Xinghua Wang, Feng Zhang
2024	J	`jnl`	A 28-nm Dual-Mode Explicit Class-F₂₃ VCO With Low-Loss CM Return Path Achieving 70-400-kHz 1/f³ PN Corner Over 4.9-7.3-GHz TR. IEEE Trans. Very Large Scale Integr. Syst. Shan Lu, DanYu Wu, Xuan Guo, Hanbo Jia, Yong Chen, Xinyu Liu
2024	—	`conf`	A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter, and -76.5-dBc Reference Spur. VLSI Technology and Circuits Tianle Chen, Hongyu Ren, Zunsong Yang, Yunbo Huang, Xianghe Meng, Weiwei Yan, Weidong Zhang, Xuqiang Zheng, Xuan Guo, Tetsuya Iizuka, Pui-In Mak, Yong Chen, Bo Li
2024	J	`jnl`	Extended Power Dynamic Range and Enhanced Power Conversion Efficiency of a Switched-Capacitor DC-DC Converter: A Tutorial. IEEE Trans. Circuits Syst. II Express Briefs Tian Siang Ho, Harikrishnan Ramiah, Kishore Kumar Pakkirisami Churchill, Yong Chen, Pui-In Mak, Rui Paulo Martins
2023	—	`conf`	A 0.0035-mm ESSCIRC Zhaoyu Zhang, Zhao Zhang, Yong Chen, Guoqing Wang, Xinyu Shen, Nan Qi, Guike Li, Shuangming Yu, Jian Liu, Nanjian Wu, Liyuan Liu
2023	J	`jnl`	A 0.004-mm IEEE J. Solid State Circuits Chenghao Zhang, Jiangbo Wei, Yong Chen, Maliang Liu, Yintang Yang
2023	J	`jnl`	A 0.0043-mm IEEE Trans. Very Large Scale Integr. Syst. Yuchen Wei, Shiheng Yang, Yueduo Liu, Rongxin Bao, Zihao Zhu, Jiahui Lin, Zehao Zhang, Yong Chen, Jun Yin, Pui-In Mak, Qiang Li
2023	J	`jnl`	A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique. IEEE Trans. Circuits Syst. I Regul. Pap. Lin Wang, Yong Chen, Chaowei Yang, Xiaoteng Zhao, Pui-In Mak, Franco Maloberti, Rui Paulo Martins
2023	—	`conf`	A 12.75-to-16-GHz Spur-Jitter-Joint-Optimization SS-PLL Achieving -94.55-dBc Reference Spur, 31.9-fs Integrated Jitter and -260.1-dB FoM. A-SSCC Yixi Li, Zhao Zhang, Yong Chen, Xinyu Shen, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu
2023	J	`jnl`	A 28-nm 368-fJ/Cycle, 0.43%/V Supply-Sensitivity, FLL-Based RC Oscillator Featuring Positive-TC-Only Resistors and ΔΣM-Based Trimming. IEEE Trans. Circuits Syst. II Express Briefs Yunbo Huang, Yong Chen, Kaiyuan Yang, Paolo Crovetti, Pui-In Mak, Rui Paulo Martins
2023	J	`jnl`	A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fs IEEE Trans. Very Large Scale Integr. Syst. Yunbo Huang, Yong Chen, Bo Zhao, Pui-In Mak, Rui Paulo Martins
2023	J	`jnl`	A 3.78-GHz Type-I Sampling PLL With a Fully Passive K IEEE Trans. Circuits Syst. I Regul. Pap. Yunbo Huang, Yong Chen, Bo Zhao, Pui-In Mak, Rui Paulo Martins
2023	—	`conf`	A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM. ESSCIRC Xinyu Shen, Zhao Zhang, Guike Li, Yong Chen, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu
2023	J	`jnl`	A 4.5-W, 18.5-24.5-GHz GaN Power Amplifier Employing Chebyshev Matching Technique. IEEE Trans. Very Large Scale Integr. Syst. Yujia Wang, Jincheng Zhang, Yong Chen, Junyan Ren, Shunli Ma
2023	J	`jnl`	A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O. IEEE Trans. Circuits Syst. I Regul. Pap. Sikai Chen, Mingyang You, Yunqi Yang, Ye Jin, Ziyi Lin, Yihong Li, Leliang Li, Guike Li, Yujun Xie, Zhao Zhang, Binhao Wang, Ningfeng Tang, Faju Liu, Zheyu Fang, Jian Liu, Nanjian Wu, Yong Chen, Liyuan Liu, Ninghua Zhu, Ming Li, Nan Qi
2023	J	`jnl`	A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation. Int. J. Circuit Theory Appl. Lin Wang, Yong Chen, Chaowei Yang, Xionghui Zhou, Mei Han, Paolo Stefano Crovetti, Pui-In Mak, Rui Paulo Martins
2023	—	`conf`	A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS. VLSI Technology and Circuits Zhao Zhang, Zhaoyu Zhang, Yong Chen, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu
2023	—	`conf`	A 72-Channel Resistive-and-Capacitive Sensor Interface Achieving 0.74 μ W/ Channel and 0.038 mm CICC Xiangdong Feng, Yuxuan Luo, Tianyi Cai, Yangfan Xuan, Yunshan Zhang, Yili Shen, Changgui Yang, Qijing Xiao, Yong Chen, Bo Zhao
2023	—	`conf`	A 880 nW, 100 kS/s, 13 bit Differential Relaxation-DAC in 180 nm. PRIME Roberto Rubino, Francesco Musolino, Yong Chen, Anna Richelli, Paolo Crovetti
2023	C	`conf`	A 9.97-GHz 190.6-dBc/Hz FOM CMOS VCO Featuring Nested Common-Mode Resonator and Intrinsic Differential 2 ISCAS Yunbo Huang, Yong Chen, Chaowei Yang, Pui-In Mak, Rui Paulo Martins
2023	J	`jnl`	A 90- to 115-GHz superheterodyne receiver front-end for W-band imaging system in 28-nm complementary metal-oxide-semiconductor. Int. J. Circuit Theory Appl. Xi Wang, Dong Wei, Zhiyang Zhang, Tianxiang Wu, Xu Chen, Yong Chen, Junyan Ren, Shunli Ma
2023	J	`jnl`	A Fully Integrated CMOS Tri-Band Ambient RF Energy Harvesting System for IoT Devices. IEEE Trans. Circuits Syst. I Regul. Pap. Jack Kee Yong, Wen Xun Lian, Harikrishnan Ramiah, Kishore Kumar Pakkirisami Churchill, Gabriel Chong, Nai Shyan Lai, Yong Chen, Pui-In Mak, Rui Paulo Martins
2023	J	`jnl`	A Fully-Integrated CMOS Dual-Band RF Energy Harvesting Front-End Employing Adaptive Frequency Selection. IEEE Access Wen Xun Lian, Harikrishnan Ramiah, Gabriel Chong, Kishore Kumar Pakkirisami Churchill, Nai Shyan Lai, Saad Mekhilef, Yong Chen, Pui-In Mak, Rui Paulo Martins
2023	J	`jnl`	A High-PCE Range-Extension CMOS Rectifier Employing Advanced Topology Amalgamation Technique for Ambient RF Energy Harvesting. IEEE Trans. Circuits Syst. II Express Briefs Alexander Choo Chia Chun, Yi Chen Lee, Harikrishnan Ramiah, Yong Chen, Pui-In Mak, Rui Paulo Martins
2023	J	`jnl`	A High-Performance Dual-Topology CMOS Rectifier With 19.5-dB Power Dynamic Range for RF-Based Hybrid Energy Harvesting. IEEE Trans. Very Large Scale Integr. Syst. Alexander Choo Chia Chun, Harikrishnan Ramiah, Kishore Kumar Pakkirisami Churchill, Yong Chen, Saad Mekhilef, Pui-In Mak, Rui Paulo Martins
2023	—	`conf`	A O.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrms Jitter, -253.8dB Jitter-Power FoM, and -76.1dBc Reference Spur. ISSCC Zhao Zhang, Xinyu Shen, Zhaoyu Zhang, Guike Li, Nan Qi, Jian Liu, Yong Chen, Nanjian Wu, Liyuan Liu
2023	J	`jnl`	A Reconfigurable CMOS Stack Rectifier With 22.8-dB Dynamic Range Achieving 47.91% Peak PCE for IoT/WSN Application. IEEE Trans. Very Large Scale Integr. Syst. Kishore Kumar Pakkirisami Churchill, Harikrishnan Ramiah, Alexander Choo Chia Chun, Gabriel Chong, Yong Chen, Pui-In Mak, Rui Paulo Martins
2023	J	`jnl`	A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-μW Embedded RRAM and Reconfigurable Strong PUF. IEEE Trans. Very Large Scale Integr. Syst. Qirui Ren, Qiang Huo, Zhisheng Chen, Qi Gao, Yiming Wang, Yiming Yang, Hao Wu, Xiangqu Fu, Xiaoxin Xu, Qing Luo, Jianfeng Gao, Chengying Chen, Xiaojin Zhao, Dengyun Lei, Xinghua Wang, Feng Zhang, Yong Chen, Pui-In Mak
2023	J	`jnl`	A Subthreshold Operation Series-Parallel Charge Pump Incorporating Dynamic Source-Fed Oscillator for Wide-Input-Voltage Energy Harvesting Application. IEEE Access Jack Kee Yong, Harikrishnan Ramiah, Kishore Kumar Pakkirisami Churchill, Gabriel Chong, Saad Mekhilef, Nai Shyan Lai, Yong Chen, Pui-In Mak, Rui Paulo Martins
2023	—	`conf`	An 83.3-to-104.7GHz Harmonic-Extraction VCO Incorporating Multi-Resonance, Multi-Core, and Multi-Mode (3M) Techniques Achieving -124dBc/Hz Absolute PN and 190.7dBc/Hz $\text{FoM}_{\mathrm{T}}$. ISSCC Hao Guo, Yong Chen, Yunbo Huang, Pui-In Mak, Rui Paulo Martins
2023	J	`jnl`	Design Trends and Perspectives of Digital Low Dropout Voltage Regulators for Low Voltage Mobile Applications: A Review. IEEE Access Li Fang Lai, Harikrishnan Ramiah, Tan Yee Chyan, Nai Shyan Lai, Chee-Cheow Lim, Yong Chen, Pui-In Mak, Rui Paulo Martins
2023	J	`jnl`	High-Performance Multiband Ambient RF Energy Harvesting Front-End System for Sustainable IoT Applications - A Review. IEEE Access Yi Chen Lee, Harikrishnan Ramiah, Alexander Choo Chia Chun, Kishore Kumar Pakkirisami Churchill, Nai Shyan Lai, Chee-Cheow Lim, Yong Chen, Pui-In Mak, Rui Paulo Martins
2023	J	`jnl`	P IEEE Trans. Circuits Syst. I Regul. Pap. Xiangqu Fu, Qirui Ren, Hao Wu, Feibin Xiang, Qing Luo, Jinshan Yue, Yong Chen, Feng Zhang
2023	J	`jnl`	Universal Stability Criterion for Type-I Sampling Phase-Locked Loops. IEEE Trans. Circuits Syst. II Express Briefs Yunbo Huang, Yong Chen, Pui-In Mak, Rui Paulo Martins
2022	J	`jnl`	A -20-dBm Sensitivity RF Energy-Harvesting Rectifier Front End Using a Transformer IMN. IEEE Trans. Very Large Scale Integr. Syst. Wen Xun Lian, Harikrishnan Ramiah, Gabriel Chong, Kishore Kumar Pakkirisami Churchill, Nai Shyan Lai, Yong Chen, Pui-In Mak, Rui Paulo Martins
2022	—	`conf`	A 0.004-mm APCCAS Yixi Li, Xinyu Shen, Zhaoyu Zhang, Guike Li, Tao Yin, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu, Yong Chen, Zhao Zhang
2022	—	`conf`	A 0.006-mm APCCAS Zhaoyu Zhang, Xinyu Shen, Yixi Li, Guike Li, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu, Yong Chen, Zhao Zhang
2022	—	`conf`	A 0.01mm ESSCIRC Paolo Crovetti, Roberto Rubino, Pedro Toledo, Francesco Musolino, Hamilton Klimach, Yong Chen, Anna Richelli
2022	J	`jnl`	A 0.0285-mm IEEE J. Solid State Circuits Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins
2022	J	`jnl`	A 0.1-V V IEEE Trans. Circuits Syst. II Express Briefs Jack Kee Yong, Harikrishnan Ramiah, Kishore Kumar Pakkirisami Churchill, Gabriel Chong, Saad Mekhilef, Yong Chen, Pui-In Mak, Rui Paulo Martins
2022	J	`jnl`	A 10-MHz to 50-GHz low-jitter multiphase clock generator for high-speed oscilloscope in 0.15-μm GaAs technology. Int. J. Circuit Theory Appl. Tianxiang Wu, Xi Wang, Yong Chen, Junyan Ren, Shunli Ma
2022	—	`conf`	A 10.8-to-37.4Gb/s Single-Loop Quarter-Rate BBCDR Without External Reference and Separate FD Featuring a Wide-Frequency-Acquisition Scheme. ICECS 2022 Lin Wang, Yong Chen, Chaowei Yang, Xiaoteng Zhao, Pui-In Mak, Franco Maloberti, Rui Paulo Martins
2022	—	`conf`	A 112-Gb/s Single-Ended PAM-4 Transceiver Front-End for Reach Extension in Long-Reach Link. ESSCIRC Xiongshi Luo, Xuewei You, Jiahan Fu, Zhenghao Li, Liping Zhong, Taiyang Fan, Zhang Qiu, Wenbo Xiao, Yong Chen, Quan Pan
2022	J	`jnl`	A 13 µW Analog Front-End with RRAM-Based Lowpass FIR Filter for EEG Signal Detection. Sensors Qirui Ren, Chengying Chen, Danian Dong, Xiaoxin Xu, Yong Chen, Feng Zhang
2022	J	`jnl`	A 13-Bit ENOB Third-Order Noise-Shaping SAR ADC Employing Hybrid Error Control Structure and LMS-Based Foreground Digital Calibration. IEEE J. Solid State Circuits Qihui Zhang, Ning Ning, Zhong Zhang, Jing Li, Kejun Wu, Yong Chen, Qi Yu
2022	J	`jnl`	A 23- to 28-GHz 5-bit switch-type phase shifter with 1-bit calibration based on optimized ABCD matrix design methods for 5G MIMO system in 0.15-μm GaAs. Int. J. Circuit Theory Appl. Zhiyang Zhang, Lihe Nie, Jincheng Zhang, Tianxiang Wu, Yong Chen, Junyan Ren, Shunli Ma
2022	—	`conf`	A 26-38GHz Ultra-Wideband Balanced Frequency Doubler in 0.15µ m GaAs pHEMT Process. APCCAS Wenyang Liu, Tianxiang Wu, Tianyang Yan, Fan Yang, Yong Chen, Shunli Ma
2022	—	`conf`	A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector. NorCAS Xinyi Ge, Yong Chen, Lin Wang, Nan Qi, Pui-In Mak, Rui Paulo Martins
2022	J	`jnl`	A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM. IEEE Trans. Very Large Scale Integr. Syst. Zunsong Yang, Yong Chen, Jia Yuan, Pui-In Mak, Rui Paulo Martins
2022	—	`conf`	A 50-Gb/s NRZ Receiver Targeting Low-Latency Multi-Chip Module Optical I/O in 45-nm SOI CMOS. APCCAS Yihong Li, Sikai Chen, Yunqi Yang, Qianli Ma, Ming Zhong, Ziyi Lin, Leliang Li, Guike Li, Zhao Zhang, Liyuan Liu, Jian Liu, Nanjian Wu, Yong Chen, Qi Peng, Nan Qi
2022	J	`jnl`	A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR. IEEE J. Solid State Circuits Qiwen Liao, Yuguang Zhang, Siyuan Ma, Lei Wang, Leliang Li, Guike Li, Zhao Zhang, Jian Liu, Nanjian Wu, Liyuan Liu, Yong Chen, Xi Xiao, Nan Qi
2022	J	`jnl`	A 56-Gb/s Reconfigurable Silicon-Photonics Transmitter Using High-Swing Distributed Driver and 2-Tap In-Segment Feed-Forward Equalizer in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Jian He, Yuguang Zhang, Han Liu, Qiwen Liao, Zhao Zhang, Miaofeng Li, Fan Jiang, Jingbo Shi, Jian Liu, Nanjian Wu, Yong Chen, Patrick Yin Chiang, Ningmei Yu, Xi Xiao, Nan Qi
2022	J	`jnl`	A 6.5-mm IEEE Trans. Circuits Syst. II Express Briefs Jincheng Zhang, Lihe Nie, Yong Chen, Junyan Ren, Shunli Ma
2022	—	`conf`	A 60-GHz CMOS Balanced Power Amplifier with Miniaturized Quadrature Hybrids Achieving 19.0-dBm Output Power and 24.4% Peak PAE. APCCAS Zhiyang Zhang, Xi Wang, Yong Chen, Junyan Ren, Shunli Ma
2022	J	`jnl`	A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components. Sensors Mengdi Zhang, Ye Zhao, Yong Chen, Paolo Crovetti, Yanji Wang, Xinshun Ning, Shushan Qiao
2022	—	`conf`	A Battery-Less Crystal-Less 49.8µW Neural-Recording Chip Featuring Two-Tone RF Power Harvesting. CICC Ziyi Chang, Changgui Yang, Yunshan Zhang, Zhuhao Li, Tianyu Zheng, Yuxuan Luo, Shaomin Zhang, Kedi Xu, Gang Pan, Bo Zhao, Yong Chen
2022	J	`jnl`	A Crystal-Less Clock Generation Technique for Battery-Free Wireless Systems. IEEE Trans. Circuits Syst. I Regul. Pap. Ziyi Chang, Yunshan Zhang, Changgui Yang, Yuxuan Luo, Sijun Du, Yong Chen, Bo Zhao
2022	C	`conf`	A Flexible-Window Filtering Technique for Interference Suppression in SpO2 Monitoring. ISCAS Xin Hu, Yuxuan Luo, Yong Chen, Bo Zhao
2022	J	`jnl`	A Fully-Integrated Ambient RF Energy Harvesting System with 423-μW Output Power. Sensors Kishore Kumar Pakkirisami Churchill, Harikrishnan Ramiah, Gabriel Chong, Yong Chen, Pui-In Mak, Rui Paulo Martins
2022	J	`jnl`	A Millimeter-Wave CMOS VCO Featuring a Mode-Ambiguity-Aware Multi-Resonant-RLCM Tank. IEEE Trans. Circuits Syst. I Regul. Pap. Hao Guo, Yong Chen, Chaowei Yang, Pui-In Mak, Rui Paulo Martins
2022	—	`conf`	A Power-Harvesting CGM Chiplet Featuring Silicon-Based Enzymatic Glucose Sensor. EMBC Ting-Hsun Wang, Zhuhao Li, Bo Liang, Yu Cai, Zhiyu Wang, Changgui Yang, Yuxuan Luo, Jiabao Sun, Xuesong Ye, Yong Chen, Bo Zhao
2022	J	`jnl`	A Reconfigurable CMOS Rectifier With 14-dB Power Dynamic Range Achieving >36-dB/mm IEEE Trans. Very Large Scale Integr. Syst. Alexander Choo Chia Chun, Harikrishnan Ramiah, Kishore Kumar Pakkirisami Churchill, Yong Chen, Saad Mekhilef, Pui-In Mak, Rui Paulo Martins
2022	J	`jnl`	A Square-Wave Stimulated DNA Analyzer Chip Featuring 120μW Power Consumption and Simultaneous Dual-Frequency Detection. IEEE Trans. Circuits Syst. II Express Briefs Xiangdong Feng, Yunshan Zhang, Yangfan Xuan, Zhuhao Li, Changgui Yang, Xin Xie, Yuxuan Luo, Xiangwei Zhao, Yong Chen, Bo Zhao
2022	J	`jnl`	A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS. IEEE J. Solid State Circuits Xiaoteng Zhao, Yong Chen, Lin Wang, Pui-In Mak, Franco Maloberti, Rui Paulo Martins
2022	J	`jnl`	APCCAS 2021 Guest Editorial. IEEE Trans. Circuits Syst. I Regul. Pap. Yong Chen, Harikrishnan Ramiah
2022	J	`jnl`	Correction: Zhang et al. A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components. Sensors 2022, 22, 5852. Sensors Mengdi Zhang, Ye Zhao, Yong Chen, Paolo Crovetti, Yanji Wang, Xinshun Ning, Shushan Qiao
2022	J	`jnl`	Design of a PAM-4 VCSEL-Based Transceiver Front-End for Beyond-400G Short-Reach Optical Interconnects. IEEE Trans. Circuits Syst. I Regul. Pap. Jian He, Donglai Lu, Haiyun Xue, Sikai Chen, Han Liu, Leliang Li, Guike Li, Zhao Zhang, Jian Liu, Liyuan Liu, Nanjian Wu, Ningmei Yu, Fengman Liu, Xi Xiao, Yong Chen, Nan Qi
2022	J	`jnl`	Evaluation and Perspective of Analog Low-Dropout Voltage Regulators: A Review. IEEE Access Tan Yee Chyan, Harikrishnan Ramiah, Sharifah Wan Muhamad Hatta, Nai Shyan Lai, Chee-Cheow Lim, Yong Chen, Pui-In Mak, Rui Paulo Martins
2022	J	`jnl`	High-Performance Harmonic-Rich Single-Core VCO With Multi-LC Tank: A Tutorial. IEEE Trans. Circuits Syst. II Express Briefs Yong Chen, Pui-In Mak, Rui Paulo Martins
2022	J	`jnl`	Low Voltage Switched-Capacitive-Based Reconfigurable Charge Pumps for Energy Harvesting Systems: An Overview. IEEE Access Tian Siang Ho, Harikrishnan Ramiah, Kishore Kumar Pakkirisami Churchill, Yong Chen, Chee-Cheow Lim, Nai Shyan Lai, Pui-In Mak, Rui Paulo Martins
2021	—	`conf`	100Gb/s PAM-4 VCSEL Driver and TIA for Short-Reach 400G-1.6T Optical Interconnects. APCCAS Donglai Lu, Jian He, Weizhong Li, Sikai Chen, Jian Liu, Nanjian Wu, Ningmei Yu, Liyuan Liu, Yong Chen, Xi Xiao, Nan Qi
2021	J	`jnl`	A 0.003-mm IEEE Trans. Circuits Syst. I Regul. Pap. Zunsong Yang, Yong Chen, Pui-In Mak, Rui Paulo Martins
2021	J	`jnl`	A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins
2021	—	`conf`	A 1.4-Vppd 64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS. ESSCIRC Chen Cai, Xuqiang Zheng, Yong Chen, DanYu Wu, Jian Luan, Lei Zhou, Jin Wu, Xinyu Liu
2021	J	`jnl`	A 1.7-to-2.7GHz 35-38% PAE Multiband CMOS Power Amplifier Employing a Digitally-Assisted Analog Pre-Distorter (DAAPD) Reconfigurable Linearization Technique. IEEE Trans. Circuits Syst. II Express Briefs Selvakumar Mariappan, Jagadheswaran Rajendran, Yong Chen, Pui-In Mak, Rui Paulo Martins
2021	J	`jnl`	A 120-150 GHz Power Amplifier in 28-nm CMOS Achieving 21.9-dB Gain and 11.8-dBm P IEEE Access Jincheng Zhang, Tianxiang Wu, Lihe Nie, Shunli Ma, Yong Chen, Junyan Ren
2021	—	`conf`	A 3-to-78GHz Differential Distributed Amplifier with Ultra- Balanced Active Balun and Gain Boosting Techniques in 65-nm CMOS Process. A-SSCC Jincheng Zhang, Tianxiang Wu, Yong Chen, Junyan Ren, Shunli Ma
2021	J	`jnl`	A 3.36-GHz Locking-Tuned Type-I Sampling PLL With -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques. IEEE Trans. Circuits Syst. II Express Briefs Yunbo Huang, Yong Chen, Hailong Jiao, Pui-In Mak, Rui Paulo Martins
2021	C	`conf`	A 3.52-GHz Harmonic-Rich-Shaping VCO with Noise Suppression and Circulation, Achieving -151-dBc/Hz Phase Noise at 10-MHz Offset. ISCAS Yunbo Huang, Yong Chen, Pui-In Mak, Rui Paulo Martins
2021	—	`conf`	A 35-to-50 GHz CMOS Low-Noise Amplifier with 22.2% -1-dB Fractional Bandwidth and 30.5-dB Maximum Gain for 5G New Radio. ESSCIRC Dong Wei, Tianxiang Wu, Shunli Ma, Yong Chen, Junyan Ren
2021	—	`conf`	A 4×25-Gb/s Serializer with Integrated CDR and 3-Tap FFE Driver for NIC Optical Interconnects. ICTA Ming Zhong, Qingwen Wang, Yong Chen, Jian Liu, Liyuan Liu, Xinghua Wang, Xiaoming Xiong, Nan Qi
2021	—	`conf`	A 4×25Gb/s De-Serializer with Baud-Rate Sampling CDR and Standing-Wave Clock Distribution for NIC Optical Interconnects. ICTA Mingyang You, Minjia Chen, Yihong Li, Guike Li, Jian Liu, Yong Chen, Yingtao Li, Nan Qi
2021	—	`conf`	A 5.0-to-6.36GHz Wideband-Harmonic-Shaping VCO Achieving 196.9dBc/Hz Peak FoM and 90-to-180kHz 1/f ISSCC Hao Guo, Yong Chen, Pui-In Mak, Rui Paulo Martins
2021	J	`jnl`	A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS. IEEE Access Manxin Li, Yuting Yao, Biao Hu, Jipeng Wei, Yong Chen, Shunli Ma, Fan Ye, Junyan Ren
2021	J	`jnl`	An accelerated architecture of change-point detection for FMCW radar mutual interference based on FPGA. Int. J. Circuit Theory Appl. Siyuan Yang, Songyi Li, Jiayan Wu, Yong Chen, Zhenyu Liu
2021	J	`jnl`	Bird's-eye view of analog and mixed-signal chips for the 21st century. Int. J. Circuit Theory Appl. Rui Paulo Martins, Pui-In Mak, Chi-Hang Chan, Jun Yin, Yan Zhu, Yong Chen, Yan Lu, Man-Kay Law, Sai-Weng Sin
2021	J	`jnl`	Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique. IEEE Access Lingshan Kong, Yong Chen, Haohong Yu, Chirn Chye Boon, Pui-In Mak, Rui Paulo Martins
2020	—	`conf`	A 0.024-mm MWSCAS Yong Chen, Pui-In Mak, Chirn Chye Boon, Rui Paulo Martins
2020	—	`conf`	A 0.0285mm CICC Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins
2020	J	`jnl`	A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector. IEEE Access Zunsong Yang, Yong Chen, Shiheng Yang, Pui-In Mak, Rui Paulo Martins
2020	J	`jnl`	A 3.3-mW 25.2-to-29.4-GHz Current-Reuse VCO Using a Single-Turn Multi-Tap Inductor and Differential-Only Switched-Capacitor Arrays With a 187.6-dBc/Hz FOM. IEEE Trans. Circuits Syst. Yunbo Huang, Yong Chen, Hao Guo, Pui-In Mak, Rui Paulo Martins
2019	J	`jnl`	A 0.0018-mm IEEE Trans. Circuits Syst. I Regul. Pap. Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins
2019	—	`conf`	A 0.003-mm A-SSCC Zunsong Yang, Yong Chen, Pui-In Mak, Rui Paulo Martins
2019	J	`jnl`	A 0.0071-mm IEEE Trans. Circuits Syst. I Regul. Pap. Yong Chen, Pui-In Mak, Zunsong Yang, Chirn Chye Boon, Rui Paulo Martins
2019	J	`jnl`	A 0.044-mm IEEE Trans. Circuits Syst. II Express Briefs Haohong Yu, Yong Chen, Chirn Chye Boon, Chenyang Li, Pui-In Mak, Rui Paulo Martins
2019	—	`conf`	A 0.08mm2 25.5-to-29.9GHz Multi-Resonant-RLCM-Tank VCO Using a Single-Turn Multi-Tap Inductor and CM-Only Capacitors Achieving 191.6dBc/Hz FoM and 130kHz 1/f3 PN Corner. ISSCC Hao Guo, Yong Chen, Pui-In Mak, Rui Paulo Martins
2019	—	`conf`	A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS. APCCAS Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins
2019	—	`conf`	A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur. ISSCC Zunsong Yang, Yong Chen, Shiheng Yang, Pui-In Mak, Rui Paulo Martins
2019	—	`conf`	A 32-Gb/s 3.53-mW/Gb/s Adaptive Receiver AFE Employing a Hybrid CTLE, Edge-DFE and Merged Data-DFE/CDR in 65-nm CMOS. APCCAS Arya Balachandran, Yong Chen, Chirn Chye Boon
2019	J	`jnl`	Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter. IEEE Trans. Very Large Scale Integr. Syst. Xinyi Ge, Yong Chen, Xiaoteng Zhao, Pui-In Mak, Rui Paulo Martins
2019	—	`conf`	Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique. APCCAS Lingshan Kong, Yong Chen, Haohong Yu, Quan Pan, Chirn Chye Boon, Pui-In Mak, Rui Paulo Martins
2018	J	`jnl`	A 0.013-mm IEEE Trans. Very Large Scale Integr. Syst. Arya Balachandran, Yong Chen, Chirn Chye Boon
2018	J	`jnl`	A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers With Maximized Timing Margin. IEEE Trans. Circuits Syst. I Regul. Pap. Yong Chen, Pui-In Mak, Chirn Chye Boon, Rui Paulo Martins
2018	J	`jnl`	A Wideband Inductorless dB-Linear Automatic Gain Control Amplifier Using a Single-Branch Negative Exponential Generator for Wireline Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Lingshan Kong, Yong Chen, Chirn Chye Boon, Pui-In Mak, Rui Paulo Martins
2015	J	`jnl`	A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable for 10-Gb/s I/O Links. IEEE Trans. Very Large Scale Integr. Syst. Yong Chen, Pui-In Mak, Yan Wang
2013	J	`jnl`	A Fifth-Order 20-MHz Transistorized-LC-Ladder LPF With 58.2-dB SFDR, 68-µW/Pole/MHz Efficiency, and 0.13-mm IEEE Trans. Circuits Syst. II Express Briefs Yong Chen, Pui-In Mak, Li Zhang, He Qian, Yan Wang
2013	J	`jnl`	A Single-Branch Third-Order Pole-Zero Low-Pass Filter With 0.014-mm IEEE Trans. Circuits Syst. II Express Briefs Yong Chen, Pui-In Mak, Stefano D'Amico, Li Zhang, He Qian, Yan Wang
2010	C	`conf`	Source-follower-based bi-quad cell for continuous-time zero-pole type filters. ISCAS Yong Chen, Pui-In Mak, Yumei Zhou