Yong-Un Jeong

26 papers A 3C 2Journal 16Unranked 5
YearRankTypeTitle / Venue / Authors
2026 J jnl
A Single-Ended MTA PAM-4 Receiver With Analog-Front-End Nonlinearity Compensation Using MTA-Error Correction Scheme for Memory Interfaces.
IEEE Access
Sanghyuk Seo, Jusung Lee, Jaeyoon Kim, Younghwan Chang, Jaekwang Yun, Yong-Un Jeong, Woo-Seok Choi
2025 — conf
An Energy and Area-Efficient PAM-4 Data Coding Scheme with Embedded Supply Noise Stabilization for Single-Ended Memory Interface.
CICC
Giyeong Heo, Younghwan Chang, Yong-Un Jeong, Jaekwang Yun, Jusung Lee, Shin-Hyun Jeong, Sanghyuk Seo, Suhwan Kim
2025 A conf
Energy-Efficient Single-Ended Capacitive PAM-4 Transceiver for Next-Generation HBM Interfaces.
ISLPED
Jaeyoon Kim, Sangyoon Lee, Jaekwang Yun, Sanghyuk Seo, Kwangyeon Lee, Yong-Un Jeong, Suhwan Kim
2025 A conf
MTA-Coded PAM-4 Receiver with Decision Feedback Power Saving Scheme and Partial DFE for Low-Power Memory Interfaces.
ISLPED
Jusung Lee, Younghwan Chang, Jaekwang Yun, Sanghyuk Seo, Yong-Un Jeong, Suhwan Kim
2024 C conf
A 0.77-pJ/bit 40-Gb/s/pin Single-Ended Hybrid DAC-Based Transmitter for Memory Interfaces.
ISCAS
Sanghyuk Seo, Yong-Un Jeong, Jaekwang Yun, Jaewook Kim, Suhwan Kim
2024 — conf
A 8Gb/s PAM-4/NRZ Dual-Mode Transmitter for Panel Interfaces with Run-length Limited Maximum Transition.
SOCC
Goeun Kim, Younghwan Chang, Yong-Un Jeong, Suhwan Kim
2024 J jnl
A Single-Ended Impedance-Matched Transmitter With Single Ring-Oscillator-Based Time-Domain ZQ Calibration for Memory Interfaces.
IEEE J. Solid State Circuits
Jaekwang Yun, Sangyoon Lee, Jaewook Kim, Joo-Hyung Chae, Suhwan Kim, Yong-Un Jeong
2024 J jnl
A Single-Ended PAM-4 Transmitter Using Unstacked Tailless CML Driver and Coefficient-Corrected FFE for Memory Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yong-Un Jeong, Joo-Hyung Chae
2024 J jnl
An N/PBTI-Isolated BTI Monitor With a Configurable Switching Network and Calibration for Process Variation in Memory Periphery.
IEEE Trans. Circuits Syst. II Express Briefs
Shin-Hyun Jeong, Yong-Un Jeong, Suhwan Kim
2024 J jnl
Per-DFE Offset Measurement and Cancellation of Weighted-VREF-Based Loop-Unrolled DFE for Memory Interfaces.
IEEE Trans. Instrum. Meas.
Yong-Un Jeong, Joo-Hyung Chae
2023 J jnl
A 0.85-pJ/b 16-Gb/s/Pin Single-Ended Transmitter With Integrated Voltage Modulation for Low-Power Memory Interfaces.
IEEE J. Solid State Circuits
Yong-Un Jeong, Joo-Hyung Chae, Suhwan Kim
2023 J jnl
Single-Ended Receiver-Side Crosstalk Cancellation With Independent Gain and Timing Control for Minimum Residual FEXT.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yong-Un Jeong, Sungphil Choi, Suhwan Kim, Joo-Hyung Chae
2022 J jnl
A 10 Gb/s/pin Single-Ended Transmitter With Reflection-Aided Duobinary Modulation for Dual-Rank Mobile Memory Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yong-Un Jeong, Sungphil Choi, Joo-Hyung Chae, Jaekwang Yun, Shin-Hyun Jeong, Suhwan Kim
2022 J jnl
A 24-Gb/s/pin Single-Ended PAM-4 Receiver With 1-Tap Decision Feedback Equalizer Using Inverter-Based Summer for Memory Interfaces.
IEEE Access
Hyunkyu Park, Yong-Un Jeong, Suhwan Kim
2022 J jnl
A Low-Power DRAM Transmitter With Phase and Current-Mode Amplitude Equalization to Improve Impedance Matching.
IEEE Trans. Circuits Syst. II Express Briefs
Sangyoon Lee, Yong-Un Jeong, Jaekwang Yun, Joo-Hyung Chae, Suhwan Kim
2022 J jnl
Design and Comparative Study of Voltage Regulation-Based 2-Tap Flexible Feed-Forward Equalizer for Voltage-Mode Transmitters.
IEEE Access
Joo-Hyung Chae, Yong-Un Jeong, Byung-Du Choi
2021 J jnl
A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface.
IEEE J. Solid State Circuits
Yong-Un Jeong, Hyunkyu Park, Changho Hyun, Joo-Hyung Chae, Shin-Hyun Jeong, Suhwan Kim
2021 J jnl
A Differentiating Receiver With a Transition-Detecting DFE for Dual-Rank Mobile Memory Interface.
IEEE Access
Sungphil Choi, Yong-Un Jeong, Joo-Hyung Chae, Shin-Hyun Jeong, Suhwan Kim
2021 C conf
A High-Accuracy and Fast-Correction Quadrature Signal Corrector Using an Adaptive Delay Gain Controller for Memory Interfaces.
ISCAS
Hyunkyu Park, Jihwan Park, Jae-Whan Lee, Yong-Un Jeong, Shin-Hyun Jeong, Suhwan Kim, Joo-Hyung Chae
2020 — conf
A 0.4-1.7GHz Wide Range Fractional-N PLL Using a Transition-Detection DAC for Jitter Reduction.
A-SSCC
Jaekwang Yun, Sangyoon Lee, Yong-Un Jeong, Shin-Hyun Jeong, Suhwan Kim
2020 — conf
A 28-Gb/s/pin PAM-4 Single-Ended Transmitter with High-Linearity and Impedance-Matched Driver and 3-Point ZQ Calibration for Memory Interfaces.
VLSI Circuits
Yong-Un Jeong, Hyunkyu Park, Changho Hyun, Suhwan Kim
2020 J jnl
A 9Gb/s Wide Output Range Transmitter With 2D Binary-Segmented Driver and Dual-Loop Calibration for Intra-Panel Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs
Yong-Un Jeong, Jihwan Park, Mino Kim, Joo-Hyung Chae, Jaekwang Yun, Hyunjoong Lee, Suhwan Kim
2020 J jnl
Data-Dependent Selection of Amplitude and Phase Equalization in a Quarter-Rate Transmitter for Memory Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap.
Joo-Hyung Chae, Yong-Un Jeong, Suhwan Kim
2019 A conf
A Low-Power and Low-Noise 20: 1 Serializer with Two Calibration Loops in 55-nm CMOS.
ISLPED
Yong-Un Jeong, Joo-Hyung Chae, Sungphil Choi, Jaekwang Yun, Shin-Hyun Jeong, Suhwan Kim
2018 J jnl
A 2.1-Gb/s 12-Channel Transmitter With Phase Emphasis Embedded Serializer for 55-in UHD Intra-Panel Interface.
IEEE J. Solid State Circuits
Jihwan Park, Joo-Hyung Chae, Yong-Un Jeong, Jae-Whan Lee, Suhwan Kim
2017 — conf
A 2.1Gbps 12-channel transmitter with phase emphasis embedded serializer for UHD intra-panel interface.
A-SSCC
Jihwan Park, Joo-Hyung Chae, Yong-Un Jeong, Jae-Whan Lee, Suhwan Kim