Yong-Bin Kim - RankMe

160 papers B 1C 5Misc 1Journal 37Unranked 113

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	A Novel Area Efficient Approximate Stochastic Computing Approach for Edge Devices. ISOCC Keerthana Pamidimukkala, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi
2023	—	`conf`	Low-Power Counters using Pathfinding Technique. ISOCC Yixuan He, Minsu Choi, Kyung-Ki Kim, Yong-Bin Kim
2023	—	`conf`	Modeling Truncation-Based Approximation Error in Stochastic Computing Circuits. ISOCC Keerthana Pamidimukkala, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi
2022	—	`conf`	A Time-Domain Parallel Counter for Deep Learning Macro. ISOCC Yixuan He, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim
2022	—	`conf`	Time-Efficient Approximate Stochastic Computing for Medical Imaging Applications. ISOCC Keerthana Pamidimukkala, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi
2021	—	`conf`	A Stray-Insensitive Low-Power Capacitive Sensor Interface with Time-Compensation Technique. MWSCAS Yixuan He, Yong-Bin Kim
2021	—	`conf`	A Time-Domain Computing-In-Memory Micro using Ring Oscillator. ISOCC Yixuan He, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim
2021	—	`conf`	FPGA-based Scalable Road Image Stochastic Denosing Approach. ISOCC Cheolhyeong Park, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi
2021	—	`conf`	Stochastic Edge Detection for Fine-Grained Progressive Precision. ISOCC Youngwook Lee, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi
2020	—	`conf`	A Tunable High-Gain Low-Noise Transimpedance Amplifier for Biosensing. MWSCAS Yixuan He, Minsu Choi, Yong-Bin Kim
2020	—	`conf`	An Ultra-Low-Power Tunable Bump Circuit using Source-Degenerated Differential Transconductor. ISOCC Yixuan He, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim
2020	—	`conf`	Gate Diffusion Input Multi-Threshold Null Convention Logic Circuit Design Approach. ISOCC Prashanthi Metku, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim
2020	—	`conf`	Peak Current Control Boost Converter with Time-Multiplex. ISOCC Elizabeth Amyouny, Yixuan He, Kyung Ki Kim, Yong-Bin Kim
2019	—	`conf`	10 GHz Standing Wave Oscillator Based Clock Distribution Network Considering Distributed Capacitance. MWSCAS Gyunam Jeon, Yong-Bin Kim
2019	—	`conf`	Area Efficient Multi-Threshold Null Convenction Logic. ISOCC Prashanthi Metku, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim
2019	—	`conf`	Evaluations of Electronic Neuron Model for Low Power VLSI Implementation. ISOCC Yixuan He, Kyung Ki Kim, Yong-Bin Kim
2019	—	`conf`	Optimization of Null Convenction Logic Using Gate Diffusion Input. ISOCC Prashanthi Metku, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim
2019	—	`conf`	Standing Wave Oscillator Based Clock Distribution Minimizing Equivalent Capacitance for Process and Temperature variation. ISOCC Gyunam Jeon, Kyung Ki Kim, Yong-Bin Kim
2018	—	`conf`	Area Efficient 4Gb/s Clock Data Recovery Using Improved Phase Interpolator with Error Monitor. MWSCAS Gyunam Jeon, Yong-Bin Kim
2018	—	`conf`	Generalized Adaptive Variable Bit Truncation Method for Approximate Stochastic Computing. ISOCC Keerthana Pamidimukkala, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi
2018	—	`conf`	Low Power Digital Temperature Sensor Using Modified Inverter Interlaced Cascaded Delay Cell. MWSCAS Yun Seok Hong, Yong-Bin Kim
2018	—	`conf`	Low-Power Null Convention Logic Multiplier Design Based On Gate Diffusion Input Technique. ISOCC Prashanthi Metku, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi
2018	J	`jnl`	Transceiver design for LVSTL signal interface with a low power on-chip self calibration scheme. Integr. Yongsuk Choi, Gyunam Jeon, Yong-Bin Kim
2017	C	`conf`	A 4Gb/s half-rate DFE with switched-cap and IIR summation for data correction. ISCAS Gyunam Jeon, Yong-Bin Kim
2017	J	`jnl`	A Two-Parameter Calibration Technique Tracking Temperature Variations for Current Source Mismatch. IEEE Trans. Circuits Syst. II Express Briefs Haiyang Zhu, Wenhua Yang, Gil Engel, Yong-Bin Kim
2017	—	`conf`	A quarter-rate 3-tap DFE for 4Gbps data rate with switched-capapctiors based 1 ISOCC Gyunam Jeon, Yong-Bin Kim
2017	J	`jnl`	Fully Integrated on-Chip Switched DC-DC Converter for Battery-Powered Mixed-Signal SoCs. Symmetry HeungJun Jeon, Kyung Ki Kim, Yong-Bin Kim
2017	—	`conf`	Global clock distribution on standing wave with CMOS active inductor loading. MWSCAS Jing Yang, Yong-Bin Kim
2017	—	`conf`	Low-power null convention logic design based on modified gate diffusion input technique. ISOCC Prashanthi Metku, Ramu Seva, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi
2017	—	`conf`	Switched Capacitor and Infinite Impulse Response Summation for a Quarter-Rate DFE with 4Gb/s Data Rate. ACM Great Lakes Symposium on VLSI Gyunam Jeon, Yong-Bin Kim
2017	—	`conf`	Time-domain temperature sensor based on interlaced hysteresis delay cells. ISOCC Yun Seok Hong, Yong-Bin Kim, Kyung Ki Kim
2017	—	`conf`	Variable bit truncation technique for approximate stochastic computing (ASC). ISOCC Ramu Seva, Prashanthi Metku, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi
2016	—	`conf`	A 100MS/s 10-bit Split-SAR ADC with Capacitor Mismatch Compensation Using Built-In Calibration. NATW Yongsuk Choi, Yong-Bin Kim, In-Seok Jung
2016	—	`conf`	A Novel On-Chip Impedance Calibration Method for LPDDR4 Interface between DRAM and AP/SoC. ACM Great Lakes Symposium on VLSI Yongsuk Choi, Yong-Bin Kim
2016	J	`jnl`	A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories. IEEE Trans. Computers Wei Wei, Kazuteru Namba, Yong-Bin Kim, Fabrizio Lombardi
2016	—	`conf`	An Area Efficient 4Gb/s Half-Rate 3-Tap DFE with Current-Integrating Summer for Data Correction. NATW Chen Zhang, Gyunam Jeon, Yongsuk Choi, Yong-Bin Kim, Kyung Ki Kim
2016	—	`conf`	Approximate stochastic computing (ASC) for image processing applications. ISOCC Ramu Seva, Prashanthi Metku, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi
2016	—	`conf`	Hybrid GDI-NCL for area/power reduction. ISOCC Prashanthi Metku, Ramu Seva, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi
2016	—	`conf`	Integrated circuits design using carbon nanotube field effect transistor. ISOCC Yong-Bin Kim
2016	—	`conf`	Parallel decoding for multi-stage BCH decoder. ISOCC Prashanthi Metku, Ramu Seva, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi
2015	—	`conf`	A 10-Gb/s receiver with a continuous-time linear equalizer and 1-tap decision-feedback equalizer. MWSCAS Yongsuk Choi, Yong-Bin Kim
2015	—	`conf`	A process tolerant semi-self impedance calibration method for LPDDR4 memory controller. MWSCAS Ho Joon Lee, Yong-Bin Kim
2015	J	`jnl`	Noise Reduction Technique Through Bandwidth Switching for Switched-Capacitor Amplifier. IEEE Trans. Circuits Syst. I Regul. Pap. Haiyang Zhu, Ron Kapusta, Yong-Bin Kim
2014	—	`conf`	A 12-bit 32MS/s SAR ADC using built-in self calibration technique to minimize capacitor mismatch. DFT In-Seok Jung, Yong-Bin Kim
2014	—	`conf`	A built-in calibration system to optimize third-order intermodulation performance of RF amplifiers. MWSCAS Yongsuk Choi, Chun-hsiang Chang, Hari Chauhan, In-Seok Jung, Marvin Onabajo, Yong-Bin Kim
2014	—	`conf`	A built-in calibration system with a reduced FFT engine for linearity optimization of low power LNA. DFT Yongsuk Choi, Chun-hsiang Chang, In-Seok Jung, Marvin Onabajo, Yong-Bin Kim
2014	—	`conf`	A low power high resolution digital PWM with process and temperature calibrations for digital controlled DC-DC converters. ACM Great Lakes Symposium on VLSI Jing Lu, Yong-Bin Kim
2014	—	`conf`	A novel mixed-signal self-calibration technique for baseband filters in systems-on-chip mobile transceivers. ACM Great Lakes Symposium on VLSI Yongsuk Choi, Yong-Bin Kim
2014	—	`conf`	A novel self-calibration scheme for 12-bit 50MS/s SAR ADC. MWSCAS In-Seok Jung, Yong-Bin Kim
2014	J	`jnl`	Accurate and Efficient On-Chip Spectral Analysis for Built-In Testing and Calibration Approaches. IEEE Trans. Very Large Scale Integr. Syst. Hari Chauhan, Yongsuk Choi, Marvin Onabajo, In-Seok Jung, Yong-Bin Kim
2014	—	`conf`	An area efficient low power high speed S-Box implementation using power-gated PLA. ACM Great Lakes Symposium on VLSI Ho Joon Lee, Yong-Bin Kim
2014	J	`jnl`	Asynchronous Advanced Encryption Standard Hardware with Random Noise Injection for Improved Side-Channel Attack Resistance. J. Electr. Comput. Eng. Siva Kotipalli, Yong-Bin Kim, Minsu Choi
2014	—	`conf`	Calibration technique tracking temperature for current-steering digital-to-analog converters. MWSCAS Haiyang Zhu, Wenhua Yang, Nathan Egan, Yong-Bin Kim
2014	—	`conf`	Full custom implementation of a S-Box circuit architecture using power gated PLA structure. MWSCAS Ho Joon Lee, Yong-Bin Kim, Kyung Ki Kim
2013	—	`conf`	A 10-bit 64MS/s SAR ADC using variable clock period method. MWSCAS In-Seok Jung, Marvin Onabajo, Yong-Bin Kim
2013	—	`conf`	A high performance modulo 2 MWSCAS Weifu Li, Yong-Bin Kim
2013	—	`conf`	A switched-capacitor DC-DC converter using delta-sigma digital pulse frequency modulation control method. MWSCAS Yongsuk Choi, HeungJun Jeon, Yong-Bin Kim
2013	—	`conf`	Low power Null Convention Logic circuit design based on DCVSL. MWSCAS Ho Joon Lee, Yong-Bin Kim
2012	J	`jnl`	A CMOS Low-Power Digital Polar Modulator System Integration for WCDMA Transmitter. IEEE Trans. Ind. Electron. In-Seok Jung, Yong-Bin Kim
2012	—	`conf`	A design and integration of Parametric Measurement Unit on to a 600MHz DCL. ISOCC Edward Collins, In-Seok Jung, Yong-Bin Kim, Kyung Ki Kim
2012	—	`conf`	A fully integrated switched-capacitor DC-DC converter with dual output for low power application. ACM Great Lakes Symposium on VLSI HeungJun Jeon, Yong-Bin Kim
2012	—	`conf`	A high speed low power modulo 2 MWSCAS He Qi, Yong-Bin Kim, Minsu Choi
2012	—	`conf`	A low stand-by power start-up circuit for SMPS PWM controller. ACM Great Lakes Symposium on VLSI In-Seok Jung, Yong-Bin Kim
2012	—	`conf`	A novel 4-to-3 step-down on-chip SC DC-DC converter with reduced bottom-plate loss. MWSCAS HeungJun Jeon, Yong-Bin Kim, Kyung Ki Kim
2012	—	`conf`	A novel sort error hardened 10T SRAM cells for low voltage operation. MWSCAS In-Seok Jung, Yong-Bin Kim, Fabrizio Lombardi
2012	—	`conf`	All-digital phased-locked loop with local passive interpolation time-to-digital converter based on a tristate inverter. MWSCAS Moon Seok Kim, Yong-Bin Kim, Kyung Ki Kim
2012	—	`conf`	Configurable logic block (CLB) design for Asynchronous Nanowire Crossbar system. MWSCAS Jun Wu, Yong-Bin Kim, Minsu Choi
2012	J	`jnl`	Design and analysis of the quadfferential amplifier. Microelectron. J. Tina Marie Rookmaaker, Moon Seok Kim, Yong-Bin Kim
2012	—	`conf`	Design and evaluation of Side Channel Attack resistant asynchronous AES Round Function. MWSCAS Siva Pavan Kumar Kotipalli, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi
2012	—	`conf`	Hardening a memory cell for low power operation by gate leakage reduction. DFT Jianping Gong, Yong-Bin Kim, Fabrizio Lombardi, Jie Han
2012	—	`conf`	Low power, high PVT variation tolerant central pattern generator design for a bio-hybrid micro robot. MWSCAS Jing Lu, Jing Yang, Yong-Bin Kim, Joseph Ayers
2012	—	`conf`	On-chip HBD sensor for nanoscale CMOS technology. MWSCAS Ho Joon Lee, Yong-Bin Kim, Kyung Ki Kim
2012	—	`conf`	Post-configuration repair strategy for asynchronous nanowire crossbar system. MWSCAS Jun Wu, Yong-Bin Kim, Minsu Choi
2012	—	`conf`	Self adaptive body biasing scheme for leakage power reduction in nanoscale CMOS circuit. ACM Great Lakes Symposium on VLSI Jing Yang, Yong-Bin Kim
2012	—	`conf`	Soft error masking latch for sub-threshold voltage operation. MWSCAS Yongsuk Choi, Yong-Bin Kim, Fabrizio Lombardi
2011	J	`jnl`	A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors. IEEE Trans. Very Large Scale Integr. Syst. Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi
2011	—	`conf`	A design approach of a Parametric Measurement Unit on to a 600MHz DCL. ISOCC Edward Collins, In-Seok Jung, Yong-Bin Kim, Kyung Ki Kim
2011	C	`conf`	Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upset. ICCD Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi
2010	—	`conf`	8Gb/s capacitive low power and high speed 4-PWAM transceiver design. ACM Great Lakes Symposium on VLSI Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi
2010	—	`conf`	A 65nm CMOS ultra low power and low noise 131M front-end transimpedance amplifier. SoCC Jiaping Hu, Yong-Bin Kim, Joseph Ayers
2010	—	`conf`	A CMOS low-power low-offset and high-speed fully dynamic latched comparator. SoCC HeungJun Jeon, Yong-Bin Kim
2010	J	`jnl`	A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops. VLSI Design Jun Zhao, Yong-Bin Kim
2010	—	`conf`	A low-offset high-speed double-tail dual-rail dynamic latched comparator. ACM Great Lakes Symposium on VLSI HeungJun Jeon, Yong-Bin Kim
2010	—	`conf`	A novel all-digital fractional-N frequency synthesizer architecture with fast acquisition and low spur. ISQED Jun Zhao, Yong-Bin Kim
2010	—	`—`	Database Support for Top-Down Proteomics Yong-Bin Kim
2010	J	`jnl`	Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability. Integr. Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi
2010	—	`conf`	High speed and low power transceiver design with CNFET and CNT bundle interconnect. SoCC Young Bok Kim, Yong-Bin Kim
2010	—	`conf`	Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems. ACM Great Lakes Symposium on VLSI Jun Wu, Yong-Bin Kim, Minsu Choi
2010	—	`conf`	Modelling a CNTFET with Undeposited CNT Defects. DFT Geunho Cho, Fabrizio Lombardi, Yong-Bin Kim
2010	—	`conf`	Performance assessment of analog circuits with carbon nanotube FET (CNFET). ACM Great Lakes Symposium on VLSI Janardhanan S. Ajit, Yong-Bin Kim, Minsu Choi
2010	—	`conf`	Read-out schemes for a CNTFET-based crossbar memory. ACM Great Lakes Symposium on VLSI Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi
2010	J	`jnl`	Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems. IEEE Trans. Instrum. Meas. HeungJun Jeon, Yong-Bin Kim, Minsu Choi
2009	J	`jnl`	A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nanoscale VLSI Systems. IEEE Trans. Very Large Scale Integr. Syst. Kyung Ki Kim, Yong-Bin Kim
2009	—	`conf`	A Novel Hardened Design of a CMOS Memory Cell at 32nm. DFT Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi
2009	J	`jnl`	A Novel Statistical Timing and Leakage Power Characterization of Partially Depleted Silicon-on-Insulator Gates. IEEE Trans. Instrum. Meas. Kyung Ki Kim, Yong-Bin Kim, Fabrizio Lombardi
2009	—	`conf`	Errors in DNA Self-Assembly by Synthesized Tile Sets. DFT Xiaojun Ma, Masoud Hashempour, Yong-Bin Kim, Fabrizio Lombardi
2009	J	`jnl`	Guest Editorial. J. Electron. Test. Cristiana Bolchini, Yong-Bin Kim
2009	Misc	`conf`	Soft-Error Hardening Designs of Nanoscale CMOS Latches. VTS Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi
2008	—	`ed.`	23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA DFT Cristiana Bolchini, Yong-Bin Kim, Dimitris Gizopoulos, Mohammad Tehranipoor
2008	—	`conf`	A low leakage 9t sram cell for ultra-low power operation. ACM Great Lakes Symposium on VLSI Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi
2008	—	`conf`	A low power 32 nanometer CMOS digitally controlled oscillator. SoCC Jun Zhao, Yong-Bin Kim
2008	J	`jnl`	Analysis and Simulation of Jitter Sequences for Testing Serial Data Channels. IEEE Trans. Ind. Informatics Kyung Ki Kim, Jing Huang, Yong-Bin Kim, Fabrizio Lombardi
2008	—	`conf`	Checkpointing of Rectilinear Growth in DNA Self-Assembly. DFT Stephen Frechette, Yong-Bin Kim, Fabrizio Lombardi
2008	—	`conf`	Low power 8T SRAM using 32nm independent gate FinFET technology. SoCC Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi
2008	J	`jnl`	Monomer Control for Error Tolerance in DNA Self-Assembly. J. Electron. Test. Byunghyun Jang, Yong-Bin Kim, Fabrizio Lombardi
2008	J	`jnl`	Standby power reduction using optimal supply voltage and body-bias voltage. IEICE Electron. Express Kyung Ki Kim, Yong-Bin Kim
2007	—	`ed.`	22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy. DFT Cristiana Bolchini, Yong-Bin Kim, Adelio Salsano, Nur A. Touba
2007	C	`conf`	A CMOS Low Power Fully Digital Adaptive Power Delivery System Based on Finite State Machine Control. ISCAS Yong-Bin Kim, Kyung Ki Kim, James T. Doyle
2007	—	`conf`	Defect-Tolerant Gate Macro Mapping & Placement in Clock-Free Nanowire Crossbar Architecture. DFT Ravi Bonam, Yong-Bin Kim, Minsu Choi
2007	—	`conf`	Fault Tolerant Source Routing for Network-on-Chip. DFT Young Bok Kim, Yong-Bin Kim
2007	J	`jnl`	Leakage Minimization Technique for Nanoscale CMOS VLSI. IEEE Des. Test Comput. Kyung Ki Kim, Yong-Bin Kim, Minsu Choi, Nohpill Park
2007	J	`jnl`	Low power CMOS electronic central pattern generator design for a biomimetic underwater robot. Neurocomputing Young-Jun Lee, Jihyun Lee, Kyung Ki Kim, Yong-Bin Kim, Joseph Ayers
2007	C	`conf`	Optimal Body Biasing for Minimum Leakage Power in Standby Mode. ISCAS Kyung Ki Kim, Yong-Bin Kim
2007	J	`jnl`	ProSight PTM 2.0: improved protein identification and characterization for top down mass spectrometry. Nucleic Acids Res. Leonid Zamdborg, Richard D. LeDuc, Kevin J. Glowacz, Yong-Bin Kim, Vinayak Viswanathan, Ian T. Spaulding, Bryan P. Early, Eric J. Bluhm, Shannee Babai, Neil L. Kelleher
2007	J	`jnl`	Ultra-low voltage high-speed Schmitt trigger circuit in SOI MOSFET technology. IEICE Electron. Express Kyung Ki Kim, Yong-Bin Kim
2006	—	`conf`	A Novel 8-Phase PLL Design for PWM Scheme in High Speed I/O Circuits. SoCC Rui Tang, Yong-Bin Kim
2006	J	`jnl`	A high-efficiency fully digital synchronous buck converter power delivery system based on a finite-state machine. IEEE Trans. Very Large Scale Integr. Syst. Woon Kang, Yong-Bin Kim, T. Doyle
2006	J	`jnl`	ASLIC: A low power CMOS analog circuit design automation. Integr. Jihyun Lee, Yong-Bin Kim
2006	J	`jnl`	Design metal-dot based QCA circuits using SPICE model. Microelectron. J. Rui Tang, Fengming Zhang, Yong-Bin Kim
2006	—	`conf`	Error Tolerance of DNA Self-Assembly by Monomer Concentration Control. DFT Byunghyun Jang, Yong-Bin Kim, Fabrizio Lombardi
2006	J	`jnl`	Evaluating the Yield of Repairable SRAMs for ATE. IEEE Trans. Instrum. Meas. Marco Ottavi, Luca Schiano, Xiaopeng Wang, Yong-Bin Kim, Fred J. Meyer, Fabrizio Lombardi
2006	—	`conf`	Inherited Redundancy and Configurability Utilization for Repairing Nanowire Crossbars with Clustered Defects. DFT Yadunandana Yellambalase, Minsu Choi, Yong-Bin Kim
2006	—	`conf`	Load Board Designs Using Compound Dot Technique and Phase Detector for Hierarchical ATE Calibrations. DFT Fengming Zhang, Warren Necoechea, Peter Reiter, Yong-Bin Kim, Fabrizio Lombardi
2006	J	`jnl`	Measuring the timing jitter of ATE in the frequency domain. IEEE Trans. Instrum. Meas. Luca Schiano, Mariam Momenzadeh, Fengming Zhang, Young-Jun Lee, Thomas Kane, Solomon Max, Philip Perkins, Yong-Bin Kim, Fabrizio Lombardi, Fred J. Meyer
2006	—	`conf`	PWAM signalling scheme for high speed serial link transceiver design. ACM Great Lakes Symposium on VLSI Rui Tang, Yong-Bin Kim
2005	—	`conf`	ASLIC: A Low Power CMOS Analog Circuit Design Automation. ISQED Jihyun Lee, Yong-Bin Kim
2005	—	`conf`	Data Dependent Jitter (DDJ) Characterization Methodology. DFT Kyung Ki Kim, Yong-Bin Kim, Fabrizio Lombardi
2005	J	`jnl`	Environmental-based characterization of SoC-based instrumentation systems for stratified testing. IEEE Trans. Instrum. Meas. Noh-Jin Park, K. M. George, Nohpill Park, Minsu Choi, Yong-Bin Kim, Fabrizio Lombardi
2005	—	`conf`	On the Modeling and Analysis of Jitter in ATE Using Matlab. DFT Kyung Ki Kim, Jing Huang, Yong-Bin Kim, Fabrizio Lombardi
2005	—	`conf`	QCA-based nano circuits design [adder design example]. ISCAS (3) Rui Tang, Fengming Zhang, Yong-Bin Kim
2005	—	`conf`	Quantum-dot cellular automata SPICE macro model. ACM Great Lakes Symposium on VLSI Rui Tang, Fengming Zhang, Yong-Bin Kim
2005	J	`jnl`	SET-based nano-circuit simulation and design method using HSPICE. Microelectron. J. Fengming Zhang, Rui Tang, Yong-Bin Kim
2004	J	`jnl`	A CMOS subbandgap reference circuit with 1-v power supply voltage. IEEE J. Solid State Circuits J. Doyle, Young Jun Lee, Yong-Bin Kim, H. Wilsch, Fabrizio Lombardi
2004	—	`conf`	A fast and precise interconnect capacitive coupling noise model. ISCAS (2) Young-Jun Lee, Yong-Bin Kim
2004	J	`jnl`	Balanced dual-stage repair for dependable embedded memory cores. J. Syst. Archit. Minsu Choi, Nohpill Park, Vincenzo Piuri, Yong-Bin Kim, Fabrizio Lombardi
2004	J	`jnl`	Fast and accurate DAC modeling techniques based on wavelet theory. Microelectron. J. James T. Doyle, Young-Jun Lee, Yong-Bin Kim
2004	—	`conf`	Fault tolerant clockless wave pipeline design. Conf. Computing Frontiers Tao Feng, Byoungjae Jin, J. Wang, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi
2004	—	`conf`	Low power real time electronic neuron VLSI design using subthreshold technique. ISCAS (4) Young-Jun Lee, Jihyun Lee, Yong-Bin Kim, Joseph Ayers, Alexander Volkovskii, Allen I. Selverston, Henry D. I. Abarbanel, Mikhail I. Rabinovich
2004	J	`jnl`	ProSight PTM: an integrated environment for protein identification and characterization by top-down mass spectrometry. Nucleic Acids Res. Richard D. LeDuc, Gregory K. Taylor, Yong-Bin Kim, Thomas E. Januszyk, Lee H. Bynum, Joseph V. Sola, John S. Garavelli, Neil L. Kelleher
2004	—	`conf`	Reliability Modeling and Assurance of Clockless Wave Pipeline. DFT Tao Feng, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi, Fred J. Meyer
2004	—	`conf`	SET-based nano-circuit simulation and design method using HSPICE. ACM Great Lakes Symposium on VLSI Fengming Zhang, Rui Tang, Yong-Bin Kim
2004	—	`conf`	SRAM word-oriented redundancy methodology using built in self-repair. SoCC Jihyun Lee, Young-Jun Lee, Yong-Bin Kim
2004	—	`conf`	Scan Test of IP Cores in an ATE Environment. DELTA Luca Schiano, Yong-Bin Kim, Fabrizio Lombardi
2003	—	`conf`	A Digital and Wide Power Bandwidth H-Field Generator for Automatic Test Equipment. DFT Fengming Zhang, Young-Jun Lee, Thomas Kane, Luca Schiano, Mariam Momenzadeh, Yong-Bin Kim, Fred J. Meyer, Fabrizio Lombardi, Solomon Max, Phil Perkinson
2003	—	`conf`	A Novel Clocking Strategy for Dynamic Circuits. ISQED Young-Jun Lee, Jong-Jin Lim, Yong-Bin Kim
2003	—	`conf`	A novel 32-bit scalable multiplier architecture. ACM Great Lakes Symposium on VLSI Yeshwant Kolla, Yong-Bin Kim, John Carter
2003	—	`conf`	An accurate DAC modeling technique based on wavelet theory. CICC James T. Doyle, Young-Jun Lee, Yong-Bin Kim
2003	J	`jnl`	Analysis and measurement of timing jitter induced by radiated EMI noise in automatic test equipment. IEEE Trans. Instrum. Meas. Young-Jun Lee, Thomas Kane, Jong-Jin Lim, Young Jun Schiano, Yong-Bin Kim, Fred J. Meyer, Fabrizio Lombardi, Solomon Max
2003	J	`jnl`	Automating Wave-Pipelined Circuit Design. IEEE Des. Test Comput. Woo Jin Kim, Yong-Bin Kim
2003	B	`conf`	Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems. NCA Minsu Choi, Noh-Jin Park, K. M. George, Byoungjae Jin, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi
2003	J	`jnl`	Guest Editors' Introduction: Clockless VLSI Systems. IEEE Des. Test Comput. Soha Hassoun, Yong-Bin Kim, Fabrizio Lombardi
2003	—	`conf`	Need For Undergraduate And Graduate-Level Education In Testing Of Microelectronic Circuits And Systems. MSE Minsu Choi, Hardy J. Pottinger, Nohpill Park, Yong-Bin Kim
2003	—	`conf`	Optimal Spare Utilization in Repairable and Reliable Memory Cores. MTDT Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri
2003	—	`conf`	Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults. DFT Tao Feng, Nohpill Park, Yong-Bin Kim, Vincenzo Piuri
2002	—	`conf`	A Test-Vector Generation Methodology for Crosstalk Noise Faults. DFT Hamidreza Hashempour, Yong-Bin Kim, Nohpill Park
2002	—	`conf`	Balanced Redundancy Utilization in Embedded Memory Cores for Dependable Systems. DFT Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri
2002	—	`conf`	Design flow of robust routed power distribution for low power ASIC. ISCAS (1) Dae Woon Kang, Yong-Bin Kim
2002	C	`conf`	Hardware/Software Co-Reliability of Configurable Digital Systems. PRDC Minsu Choi, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi
2001	—	`conf`	Analog MAP Decoder for (8, 4) Hamming Code in Subthreshold CMOS. ARVLSI Chris Winstead, Jie Dai, Woo Jin Kim, Scott Little, Yong-Bin Kim, Chris J. Myers, Christian Schlegel
1997	—	`conf`	A CMOS delayed locked loop (DLL) for reducing clock skew to under 500 ps. ASP-DAC Yong-Bin Kim, Tom Chen