Yoji Kajitani

68 papers A* 2A 8B 2C 3Misc 1Journal 23Unranked 26
YearRankTypeTitle / Venue / Authors
2016 — ch.
Floorplan and Placement.
Encyclopedia of Algorithms
Yoji Kajitani
2013 — conf
Coding the objects in place and route CAD.
ISPD
Yoji Kajitani
2013 J jnl
Escaped Boundary Pins Routing for High-Speed Boards.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ching-Yu Chin, Chung-Yi Kuan, Tsung-Ying Tsai, Hung-Ming Chen, Yoji Kajitani
2011 A conf
On routing fixed escaped boundary pins for high speed boards.
DATE
Tsung-Ying Tsai, Ren-Jie Lee, Ching-Yu Chin, Chung-Yi Kuan, Hung-Ming Chen, Yoji Kajitani
2008 — ch.
Floorplan and Placement.
Encyclopedia of Algorithms
Yoji Kajitani
2007 J jnl
A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani
2006 — conf
A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os.
FPT
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani
2006 — conf
Adaptive Porting of Analog IPs with Reusable Conservative Properties.
ISVLSI
Takashi Nojima, Nobuto Ono, Shigetoshi Nakatake, Toru Fujimura, Koji Okazaki, Yoji Kajitani
2006 — conf
How does partitioning matter for 3D floorplanning?
ACM Great Lakes Symposium on VLSI
Tan Yan, Qing Dong, Yasuhiro Takashima, Yoji Kajitani
2006 J jnl
The Oct-Touched Tile: A New Architecture for Shape-Based Routing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani
2006 C conf
Theory of placement by numDAG related with single-sequence, SP, BSG, and O-tree.
ISCAS
Yoji Kajitani
2005 — conf
A new approach based on LFF for optimization of dynamic hardware reconfigurations.
ISCAS (2)
Zhe Zhou, Sheqin Dong, Xianlong Hong, Yuliang Wu, Yoji Kajitani
2005 J jnl
Equidistance routing in high-speed VLSI layout design.
Integr.
Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi
2005 — conf
Fixed-outline floorplanning with constraints through instance augmentation.
ISCAS (2)
Rong Liu, Sheqin Dong, Xianlong Hong, Yoji Kajitani
2005 — conf
The oct-touched tile: a new architecture for shape-based routing.
ACM Great Lakes Symposium on VLSI
Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani
2004 — conf
A device-level placement with multi-directional convex clustering.
ACM Great Lakes Symposium on VLSI
Takashi Nojima, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani
2004 — conf
Abstraction and optimization of consistent floorplanning with pillar block constraints.
ASP-DAC
Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani
2004 — conf
Equidistance routing in high-speed VLSI layout design.
ACM Great Lakes Symposium on VLSI
Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi
2004 — conf
Multi-level placement with circuit schema based clustering in analog IC layouts.
ASP-DAC
Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani
2004 — conf
Space-planning: placement of modules with controlled empty area by single-sequence.
ASP-DAC
Xuliang Zhang, Yoji Kajitani
2004 — conf
Theory of T-junction floorplans in terms of single-sequence.
ISCAS (5)
Xuliang Zhang, Yoji Kajitani
2003 J jnl
An Incremental Wiring Algorithm for VLSI Layout Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita
2003 — conf
An extended representation of Q-sequence for optimizing channel-adjacency and routing-cost.
ASP-DAC
Changwen Zhuang, Keishi Sakanushi, Liyan Jin, Yoji Kajitani
2002 A conf
An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees.
DATE
Changwen Zhuang, Yoji Kajitani, Keishi Sakanushi, Liyan Jin
2002 J jnl
An Improvement of Network-Flow Based Multi-Way Circuit Partitioning Algorithm.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kengo R. Azegami, Masato Inagi, Atsushi Takahashi, Yoji Kajitani
2002 — conf
Chip size estimation based on wiring area.
APCCAS (2)
Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita
2002 J jnl
Consistent floorplanning with hierarchical superconstraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani
2002 — conf
Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts.
ASP-DAC/VLSI Design
Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita
2002 — conf
On the equivalence of the sequence pair for rectangle packing to the dimension of partial orders [floorplanning].
APCCAS (2)
Hiroshi Miyashita, Yoji Kajitani
2002 J jnl
Recognition of Floorplan by Parametric BSG for Reuse of Layout Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Keishi Sakanushi, Zhonglin Wu, Yoji Kajitani
2001 — conf
Consistent floorplanning with super hierarchical constraints.
ISPD
Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani
2000 Misc conf
Partition, Packing and Clock Distribution-A New Paradigm of Physical Design.
VLSI Design
Yoji Kajitani, Atsushi Takahashi, Kengo R. Azegami, Shigetoshi Nakatake
2000 — conf
Self-reforming routing for stochastic search in VLSI interconnection layout.
ASP-DAC
Yukiko Kubo, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani
1999 — conf
Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion.
ASP-DAC
Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani
1998 — conf
Air-Pressure-Model-Based Fast Algorithms for General Floorplan.
ASP-DAC
Tomonori Izumi, Atsushi Takahashi, Yoji Kajitani
1998 J jnl
Approximating Steiner trees in graphs with restricted weights.
Networks
Magnús M. Halldórsson, Shuichi Ueno, Hiroshi Nakao, Yoji Kajitani
1998 — conf
Module Placement on BSG-Structure with Pre-Placed Modules and Rectilinear Modules.
ASP-DAC
Shigetoshi Nakatake, Masahiro Furuya, Yoji Kajitani
1998 J jnl
Module packing based on the BSG-structure and IC layout applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani
1998 A conf
The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications.
ICCAD
Shigetoshi Nakatake, Keishi Sakanushi, Yoji Kajitani, Masahiro Kawakita
1998 A conf
The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks.
ICCAD
Keishi Sakanushi, Shigetoshi Nakatake, Yoji Kajitani
1997 — conf
A mapping from sequence-pair to rectangular dissection.
ASP-DAC
Hiroshi Murata, Kunihiro Fujiyoshi, Tomomi Watanabe, Yoji Kajitani
1997 A conf
Clock-tree routing realizing a clock-schedule for semi-synchronous circuits.
ICCAD
Atsushi Takahashi, Kazunori Inoue, Yoji Kajitani
1997 J jnl
Design of minimum and uniform bipartites for optimum connection blocks of FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu
1997 — conf
Performance and reliability driven clock scheduling of sequential logic circuits.
ASP-DAC
Atsushi Takahashi, Yoji Kajitani
1996 — conf
Detailed-Routability of FPGAs with Extremal Switch-Block Structures.
ED&TC
Yasuhiro Takashima, Atsushi Takahashi, Yoji Kajitani
1996 A conf
Module placement on BSG-structure and IC layout applications.
ICCAD
Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani
1996 J jnl
VLSI module placement based on rectangle-packing by the sequence-pair.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani
1995 J jnl
Mixed Searching and Proper-Path-Width.
Theor. Comput. Sci.
Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani
1995 A conf
Rectangle-packing-based module placement.
ICCAD
Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani
1994 A conf
Channel-driven global routing with consistent placement (extended abstract).
ICCAD
Shigetoshi Nakatake, Yoji Kajitani
1994 C conf
Design of Optimum Totally Perfect Connection-Blocks of FPGA.
ISCAS
Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu
1994 J jnl
Minimal acyclic forbidden minors for the family of graphs with bounded path-width.
Discret. Math.
Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani
1994 B conf
New Approximation Results on Graph Matching and related Problems.
WG
Yoji Kajitani, Jun Dong Cho, Majid Sarrafzadeh
1994 B conf
The Totally-Perfect Bipartite Graph and Its Construction.
ISAAC
Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu
1993 J jnl
Generalization of aTheorem on the Parametric Maximum Flow Problem.
Discret. Appl. Math.
Tadashi Arai, Shuichi Ueno, Yoji Kajitani
1993 C conf
Optimal single hop multiple bus networks.
ISCAS
Wayne Wei-Ming Dai, Yoji Kajitani, Yorihiko Hirata
1993 — ch.
The Virtual Dimensions of a Straight Line Embedding of a plane Graph.
Algorithmic Aspects of VLSI Layout
Toshihiko Takahashi, Yoji Kajitani
1992 J jnl
Peel-the-box: a concept of switch-box routing and tractable problems.
Integr.
Atsushi Takahashi, Yoji Kajitani
1991 — conf
Mixed-Searching and Proper-Path-Width.
ISA
Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani
1988 J jnl
Minimum augmentation of a tree to a K-edge-connected graph.
Networks
Shuichi Ueno, Yoji Kajitani, Hajime Wada
1988 J jnl
On the nonseparating independent set problem and feedback set problem for graphs with no vertex degree exceeding three.
Discret. Math.
Shuichi Ueno, Yoji Kajitani, Shin'ya Gotoh
1988 J jnl
Ordering of the elements of a matroid such that its consecutive w elements are independent.
Discret. Math.
Yoji Kajitani, Shuichi Ueno, Hiroshi Miyano
1986 J jnl
Characterization of partial 3-trees in terms of three structures.
Graphs Comb.
Yoji Kajitani, Akio Ishizuka, Shuichi Ueno
1986 J jnl
The minimum augmentation of a directed tree to a
Networks
Yoji Kajitani, Shuichi Ueno
1984 J jnl
A matroid generalization of theorems of Lewin and Gallai.
Discret. Appl. Math.
Yoji Kajitani, Shuichi Ueno
1984 A* conf
The channel expansion problem in layout design.
DAC
Rachel R. Chen, Yoji Kajitani
1983 J jnl
Order of Channels for Safe Routing and Optimal Compaction of Routing Area.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yoji Kajitani
1979 A* conf
The minimum width routing of A 2-row 2-layer polycell-layout.
DAC
Tatsuya Kawamoto, Yoji Kajitani