Yoichi Koyanagi

26 papers A* 1Journal 4Unranked 21

Year	Rank	Type	Title / Venue / Authors
2016	—	`conf`	24 to 34-Gb/s ×4 multi-rate VCSEL-based optical transceiver with referenceless CDR. OFC Yukito Tsunoda, Takayuki Shibasaki, Hideki Oku, Jun Matsui, Takashi Shiraishi, Satoshi Ide, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura
2016	—	`conf`	3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS. ISSCC Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Shigeaki Kawai, Tomoyuki Arai, Hirohito Higashi, Naoaki Naka, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura
2016	—	`conf`	A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS. VLSI Circuits Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Noriaki Shirai, Shigeaki Kawai, Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura, Yutaka Ide, Kazuhiro Terashima, Hirohito Higashi, Tomokazu Higuchi, Naoaki Naka
2015	—	`conf`	22.2 A 25Gb/s hybrid integrated silicon photonic transceiver in 28nm CMOS and SOI. ISSCC Yanfei Chen, Masaya Kibune, Asako Toda, Akinori Hayakawa, Tomoyuki Akiyama, Shigeaki Sekiguchi, Hiroji Ebe, Nobuhiro Imaizumi, Tomoyuki Akahoshi, Suguru Akiyama, Shinsuke Tanaka, Takasi Simoyama, Ken Morito, Takuji Yamamoto, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura
2015	—	`conf`	22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS. ISSCC Takayuki Shibasaki, Yukito Tsunoda, Hideki Oku, Satoshi Ide, Toshihiko Mori, Yoichi Koyanagi, Kazuhiro Tanaka, Tomohiro Ishihara, Hirotaka Tamura
2015	—	`conf`	22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS. ISSCC Yukito Tsunoda, Takayuki Shibasaki, Satoshi Ide, Toshihiko Mori, Yoichi Koyanagi, Kazuhiro Tanaka, Tomohiro Ishihara, Hirotaka Tamura
2015	—	`conf`	25.78-Gb/s VCSEL-based optical transceiver with retimer-embedded driver and receiver ICs. OFC Yukito Tsunoda, Takayuki Shibasaki, Hideki Oku, Satoshi Ide, Toshihiko Mori, Yoichi Koyanagi, Kazuhiro Tanaka, Tomohiro Ishihara, Hirotaka Tamura
2014	—	`conf`	A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution. VLSIC Takushi Hashida, Yasumoto Tomita, Yuuki Ogata, Kosuke Suzuki, Shigeto Suzuki, Takanori Nakao, Yuji Terao, Satofumi Honda, Sota Sakabayashi, Ryuichi Nishiyama, Akihiko Konmoto, Yoshitomo Ozeki, Hiroyuki Adachi, Hisakatsu Yamaguchi, Yoichi Koyanagi, Hirotaka Tamura
2014	—	`conf`	A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS. VLSIC Takayuki Shibasaki, Win Chaivipas, Yanfei Chen, Yoshiyasu Doi, Takayuki Hamada, Hideki Takauchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura
2014	J	`jnl`	The 10th Generation 16-Core SPARC64™ Processor for Mission Critical UNIX Server. IEEE J. Solid State Circuits Ryuji Kan, Tomohiro Tanaka, Go Sugizaki, Kinya Ishizaka, Ryuichi Nishiyama, Sota Sakabayashi, Yoichi Koyanagi, Ryuji Iwatsuki, Kazumi Hayasaka, Taiki Uemura, Gaku Ito, Yoshitomo Ozeki, Hiroyuki Adachi, Kazuhiro Furuya, Tsuyoshi Motokurumada
2013	—	`conf`	32Gb/s 28nm CMOS time-interleaved transmitter compatible with NRZ receiver with DFE. ISSCC Yuuki Ogata, Yasuo Hidaka, Yoichi Koyanagi, Sadanori Akiya, Yuji Terao, Kosuke Suzuki, Keisuke Kashiwa, Masanobu Suzuki, Hirotaka Tamura
2013	—	`conf`	32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS. ISSCC Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura
2013	—	`conf`	A 10 ISSCC Ryuji Kan, Tomohiro Tanaka, Go Sugizaki, Ryuichi Nishiyama, Sota Sakabayashi, Yoichi Koyanagi, Ryuji Iwatsuki, Kazumi Hayasaka, Taiki Uemura, Gaku Ito, Yoshitomo Ozeki, Hiroyuki Adachi, Kazuhiro Furuya, Tsuyoshi Motokurumada
2013	J	`jnl`	A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process. IEEE J. Solid State Circuits Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura
2013	—	`conf`	A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS. ISSCC Samir Parikh, Tony Kao, Yasuo Hidaka, Jian Jiang, Asako Toda, Scott McLeod, William W. Walker, Yoichi Koyanagi, Toshiyuki Shibuya, Jun Yamada
2011	—	`conf`	A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel. ISSCC Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Takashi Miyoshi, Hideki Osone, Samir Parikh, Subodh M. Reddy, Toshiyuki Shibuya, Yasushi Umezawa, William W. Walker
2010	—	`conf`	A Single-Chip, 10-Gigabit Ethernet Switch LSI for Energy-Efficient Blade Servers. GreenCom/CPSCom Yukihiro Nakagawa, Takeshi Shimizu, Yoichi Koyanagi, Osamu Shiraki, Shinji Kobayashi, Kazuki Hyoudou, Takashi Miyoshi, Yuuki Ogata, Yasushi Umezawa, Takeshi Horie, Akira Hattori
2009	J	`jnl`	A 4-Channel 1.25-10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control. IEEE J. Solid State Circuits Yasuo Hidaka, Weixin Gai, Takeshi Horie, Jian Hong Jiang, Yoichi Koyanagi, Hideki Osone
2009	—	`conf`	A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control. ISSCC Yasuo Hidaka, Weixin Gai, Takeshi Horie, Jian Hong Jiang, Yoichi Koyanagi, Hideki Osone
2007	—	`conf`	A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer. ISSCC Yasuo Hidaka, Weixin Gai, Akira Hattori, Takeshi Horie, Jian Jiang, Kouichi Kanda, Yoichi Koyanagi, Satoshi Matsubara, Hideki Osone
2007	—	`conf`	Design Consideration of 6.25 Gbps Signaling for High-Performance Server. ASP-DAC Jian Hong Jiang, Weixin Gai, Akira Hattori, Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Hideki Osone
2001	—	`conf`	Synfinity II-a high-speed interconnect with 2 GBytes/sec self-configurable physical link. Hot Interconnects Yoichi Koyanagi, Takeshi Horie, Takashi Miyoshi, Mitsuo Ishii
1996	J	`jnl`	Fault-Tolerant Design of Neural Networks for Solving Optimization Problems. IEEE Trans. Computers Yoshihiro Tohma, Yoichi Koyanagi
1994	A*	`conf`	AP1000+: Architectural Support of PUT/GET Interface for Parallelizing Compiler. ASPLOS Kenichi Hayashi, Tsunehisa Doi, Takeshi Horie, Yoichi Koyanagi, Osamu Shiraki, Nobutaka Imamura, Toshiyuki Shimizu, Hiroaki Ishihata, Tatsuya Shindo
1993	—	`conf`	Design of Neural Networks to Tolerate the Mixture of Two Types of Faults. FTCS Yoshihiro Tohma, Yoichi Koyanagi
1992	—	`conf`	Fault Tolerant Neural Networks in Optimization Problems. FTCS Yoichi Koyanagi, Yoshihiro Tohma