Yogesh Singh Chauhan

86 papers A* 2A 5B 1C 4Misc 9Journal 39Unranked 26
YearRankTypeTitle / Venue / Authors
2026 J jnl
Evaluation of Radiation Resilience, Performance, and V
IEEE Trans. Computers
Hafeez Raza, Mahdi Benkhelifa, Koshal Kumar, Shivendra Singh Parihar, Yogesh Singh Chauhan, Hussam Amrouch, Avinash Lahgere
2026 J jnl
Ferroelectric Digital In-Memory Computing for Scalable, Reliable, and Efficient Similarity Computation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Anirban Kar, Albi Mema, Thorgund Nemec, Stefan Dünkel, Halid Mulaosmanovic, Sven Beyer, Yogesh Singh Chauhan, Hussam Amrouch
2026 J jnl
Self-Heating and Parasitic Effects in Multi-Tier CFET Design.
CoRR
Sufia Shahin, Mahdi Benkhelifa, Yogesh Singh Chauhan, Hussam Amrouch
2025 J jnl
A Lightweight PUF-Based Weights Obfuscation Technique for Secure In-Memory AI Inference.
IEEE Trans. Circuits Syst. I Regul. Pap.
Luca Parrini, Anirban Kar, Benjamin Hettwer, Taha Soliman, Yogesh Singh Chauhan, Hussam Amrouch, Norbert Wehn
2025 C conf
Benchmarking Cryogenic Circuits using 5 nm FinFETs for Quantum Processing.
ISCAS
Anirban Kar, Shivendra Singh Parihar, Florian Klemme, Yogesh Singh Chauhan, Hussam Amrouch
2025 J jnl
Cryo-CACTI: Cryogenic-Aware CACTI for Cache Modeling Down to 10K in Advanced 7nm FinFETs.
IEEE Trans. Computers
Divya Praneetha Ravipati, Victor M. van Santen, Shivendra Singh Parihar, Yogesh Singh Chauhan, Preeti Ranjan Panda, Hussam Amrouch
2025 J jnl
Exploiting drain-erase scheme in ferroelectric FETs for logic-in-memory.
Neuromorph. Comput. Eng.
Musaib Rafiq, Yogesh Singh Chauhan, Shubham Sahay
2025 J jnl
Ferroelectric FET-Based Bayesian Inference Engine for Disease Diagnosis.
IEEE Trans. Circuits Syst. I Regul. Pap.
Arka Chakraborty, Musaib Rafiq, Yawar Hayat Zarkob, Yogesh Singh Chauhan, Shubham Sahay
2025 A conf
Pushing the Boundaries of AI Chips: From Monolithic 3D CMOS to Cryogenic Computing.
DATE
Mahdi Benkhelifa, Shivendra Singh Parihar, Anirban Kar, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch
2025 B conf
Self-Aware Silicon: Enhancing Lifecycle Management with Intelligent Testing and Data Insights.
ETS
Fabian Vargas, Marko S. Andjelkovic, Milos Krstic, Anirban Kar, Swati Deshwal, Yogesh Singh Chauhan, Hussam Amrouch, Daniel Tille, Sebastian Huhn
2025 A conf
Transistor-to-GDS Reliability Analysis in Sub-3nm: Impact of Self-Heating and Aging on Timing.
ISLPED
Swati Deshwal, Hadi Nour Eddine, Mahdi Benkhelifa, Albi Mema, Yogesh Singh Chauhan, Hussam Amrouch
2024 J jnl
Design and experimental validation of class-F-1 GaN power amplifier using a compact harmonic control unit.
Microelectron. J.
Mohammad Zaid, Mohammad Sajid Nazir, Raghavendra Dangi, Yogesh Singh Chauhan
2024 J jnl
Energy-Efficient Cryogenic Ternary Content Addressable Memory using Ferroelectric SQUID.
CoRR
Shamiul Alam, Simon Thomann, Shivendra Singh Parihar, Yogesh Singh Chauhan, Kai Ni, Hussam Amrouch, Ahmedullah Aziz
2024 — conf
Enhancing the Capabilities of Quantum Transport Simulations Utilizing Machine Learning Strategies.
MLCAD
Ateeb Naseer, Yawar Hayat Zarkob, Musaib Rafiq, Mohammad Sajid Nazir, Owais Ahmad, Amit Agarwal, Somnath Bhowmick, Yogesh Singh Chauhan
2024 J jnl
GaN-based wide-band high-efficiency power amplifier with multi harmonic resonance.
Microelectron. J.
Mohammad Zaid, Ahtisham Pampori, Mohammad Sajid Nazir, Yogesh Singh Chauhan
2024 — conf
Hybrid FETs Based on Monolayer ZrI2 for Energy-Efficient Logic Applications.
DRC
Ateeb Naseer, Keshari Nandan, Amit Agarwal, Somnath Bhowmick, Yogesh Singh Chauhan
2024 — conf
Impact of Multi-Domain Microscopic Interactions on Magnetic Tunnel Junction's Static and Transient Characteristics.
DRC
Nilesh Pandey, Yogesh Singh Chauhan, Leonard F. Register, Sanjay Kumar Banerjee
2024 — conf
Impact of Multi-Domain on Ferroelectric Tunnel Junction Design Metrics.
DRC
Nilesh Pandey, Yogesh Singh Chauhan, Leonard F. Register, Sanjay Kumar Banerjee
2024 — conf
Impact of Self-Heating in 5nm FinFETs at Cryogenic Temperatures for Reliable Quantum Computing: Device-Circuit Interaction.
IRPS
Shivendra Singh Parihar, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch
2024 — conf
Innovations in Hardware Security: Leveraging FeFET Technology for Future Opportunities.
APCCAS
Anirban Kar, Yogesh Singh Chauhan, Hussam Amrouch
2024 — conf
On the Severity of Self-Heating in FDSOI at Cryogenic Temperatures: In-depth Analysis from Transistors to Full Processor.
IRPS
Anirban Kar, Florian Klemme, Yogesh Singh Chauhan, Hussam Amrouch
2024 J jnl
Optimizing Low Noise Amplifiers: A Two-Stage Approach for Improved Noise Figure and Stability.
IEEE Access
Mohammad Zaid, Purnima Kumari, Ahtisham Pampori, Mohammad Sajid Nazir, Umakant Goyal, Meena Mishra, Yogesh Singh Chauhan
2024 — conf
Technology Mapping for Cryogenic CMOS Circuits.
ISVLSI
Benjamin Hien, Marcel Walter, Victor M. van Santen, Florian Klemme, Shivendra Singh Parihar, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch, Robert Wille
2024 J jnl
Thermal Effects on Monolithic 3D Ferroelectric Transistors for Deep Neural Networks Performance.
Adv. Intell. Syst.
Shubham Kumar, Yogesh Singh Chauhan, Hussam Amrouch
2023 — conf
5nm FinFET Cryogenic SRAM Evaluation for Quantum Computing.
DRC
Shivendra Singh Parihar, Simon Thomann, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch
2023 J jnl
A Computationally Efficient Compact Model for Ferroelectric Switching With Asymmetric Nonperiodic Input Signals.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Amol D. Gaidhane, Raghvendra Dangi, Shubham Sahay, Amit Verma, Yogesh Singh Chauhan
2023 J jnl
An Ultra-Low Noise Figure and Multi-Band Re-Configurable Low Noise Amplifier.
IEEE Trans. Circuits Syst. I Regul. Pap.
Neha Bajpai, Paramita Maity, Manish Shah, Amitava Das, Yogesh Singh Chauhan
2023 J jnl
Compact and High-Performance TCAM Based on Scaled Double-Gate FeFETs.
CoRR
Liu Liu, Shubham Kumar, Simon Thomann, Yogesh Singh Chauhan, Hussam Amrouch, Xiaobo Sharon Hu
2023 J jnl
Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shubham Kumar, Swetaki Chatterjee, Simon Thomann, Yogesh Singh Chauhan, Hussam Amrouch
2023 J jnl
Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shivendra Singh Parihar, Victor M. van Santen, Simon Thomann, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch
2023 J jnl
Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs.
IEEE Open J. Circuits Syst.
Shivendra Singh Parihar, Simon Thomann, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch
2023 A* conf
Design Automation for Cryogenic CMOS Circuits.
DAC
Victor M. van Santen, Marcel Walter, Florian Klemme, Shivendra Singh Parihar, Girish Pahwa, Yogesh Singh Chauhan, Robert Wille, Hussam Amrouch
2023 J jnl
FerroCoin: Ferroelectric Tunnel Junction-Based True Random Number Generator.
IEEE Trans. Emerg. Top. Comput.
Swetaki Chatterjee, Nikhil Rangarajan, Satwik Patnaik, Dinesh Rajasekharan, Ozgur Sinanoglu, Yogesh Singh Chauhan
2023 C conf
Frontiers in AI Acceleration: From Approximate Computing to FeFET Monolithic 3D Integration.
VLSI-SoC
Shubham Kumar, Paul R. Genssler, Somaya Mansour, Yogesh Singh Chauhan, Hussam Amrouch
2023 A conf
Invited Paper: Ultra-Efficient Edge AI Using FeFET-based Monolithic 3D Integration.
ICCAD
Shubham Kumar, Yogesh Singh Chauhan, Hussam Amrouch
2023 J jnl
Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET.
CoRR
Zijian Zhao, Shan Deng, Swetaki Chatterjee, Zhouhang Jiang, Muhammad Shaffatul Islam, Yi Xiao, Yixin Xu, Scott Meninger, Mohamed Mohamed, Rajiv V. Joshi, Yogesh Singh Chauhan, Halid Mulaosmanovic, Stefan Dünkel, Dominik Kleimaier, Sven Beyer, Hussam Amrouch, Vijaykrishnan Narayanan, Kai Ni
2023 J jnl
Robust Compact Model of High-Voltage MOSFET's Drift Region.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Girish Pahwa, Ayushi Sharma, Ravi Goel, Garima Gill, Harshit Agarwal, Yogesh Singh Chauhan, Chenming Hu
2023 J jnl
SCANet: Securing the Weights With Superparamagnetic-MTJ Crossbar Array Networks.
IEEE Trans. Neural Networks Learn. Syst.
Dinesh Rajasekharan, Nikhil Rangarajan, Satwik Patnaik, Ozgur Sinanoglu, Yogesh Singh Chauhan
2022 — conf
A GaN Based Reverse Recovery Time Limiter Circuit Integrated with a Low Noise Amplifier.
VDAT
Neha Bajpai, Yogesh Singh Chauhan
2022 — conf
A Novel Approach to Mitigate Power Side-Channel Attacks for Emerging Negative Capacitance Transistor Technology.
NEWCAS
Shubham Kumar, Swetaki Chatterjee, Chetan K. Dabhi, Hussam Amrouch, Yogesh Singh Chauhan
2022 — conf
A width-scalable SPICE compact model for GaN HEMTs including self-heating effect.
DRC
Raghvendra Dangi, Ahtisham Pampori, Pragya Kushwaha, Ekta Yadav, Santanu Sinha, Yogesh Singh Chauhan
2022 J jnl
Analytical approximation of surface potential and analysis of C-V characteristics of bulk MOSFETs at cryogenic temperatures.
Microelectron. J.
Wajid Manzoor, Aloke K. Dutta, Yogesh Singh Chauhan
2022 — conf
Asymmetric Double-Gate Ferroelectric FET to Decouple the Tradeoff Between Thickness Scaling and Memory Window.
VLSI Technology and Circuits
Zhouhang Jiang, Yi Xiao, Swetaki Chatterjee, Halid Mulaosmanovic, Stefan Dünkel, Steven Soss, Sven Beyer, Rajiv V. Joshi, Yogesh Singh Chauhan, Hussam Amrouch, Vijaykrishnan Narayanan, Kai Ni
2022 C conf
Cross-layer FeFET Reliability Modeling for Robust Hyperdimensional Computing.
VLSI-SoC
Shubham Kumar, Swetaki Chatterjee, Simon Thomann, Paul R. Genssler, Yogesh Singh Chauhan, Hussam Amrouch
2022 J jnl
Ferroelectric FET-Based Implementation of FitzHugh-Nagumo Neuron Model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Dinesh Rajasekharan, Amol D. Gaidhane, Amit Ranjan Trivedi, Yogesh Singh Chauhan
2022 — conf
Impact of Corner Rounding on Quantum Confinement in GAA Nanosheet FETs for Advanced Technology Nodes.
DRC
Anirban Kar, Swapna Sarker, Avirup Dasgupta, Yogesh Singh Chauhan
2022 J jnl
Impact of NCFET Technology on Eliminating the Cooling Cost and Boosting the Efficiency of Google TPU.
IEEE Trans. Computers
Sami Salamin, Georgios Zervakis, Florian Klemme, Hammam Kattan, Yogesh Singh Chauhan, Jörg Henkel, Hussam Amrouch
2022 C conf
Novel FDSOI-based Dynamic XNOR Logic for Ultra-Dense Highly-Efficient Computing.
ISCAS
Shubham Kumar, Swetaki Chatterjee, Chetan Kumar Dabhi, Hussam Amrouch, Yogesh Singh Chauhan
2022 — conf
Self-Heating characterization and modeling of 5nm technology node FinFETs.
DRC
Shivendra Singh Parihar, Jun Z. Huang, Weike Wang, Kimihiko Imura, Yogesh Singh Chauhan
2021 J jnl
A Low Noise Power Amplifier MMIC to Mitigate Co-Site Interference in 5G Front End Modules.
IEEE Access
Neha Bajpai, Ahtisham Pampori, Paramita Maity, Manish Shah, Amitava Das, Yogesh Singh Chauhan
2021 J jnl
Impact of NCFET on Neural Network Accelerators.
IEEE Access
Georgios Zervakis, Iraklis Anagnostopoulos, Sami Salamin, Yogesh Singh Chauhan, Jörg Henkel, Hussam Amrouch
2021 J jnl
Improved modeling of flicker noise including velocity saturation effect in FinFETs and experimental validation.
Microelectron. J.
Ravi Goel, Weike Wang, Yogesh Singh Chauhan
2021 J jnl
On the Resiliency of NCFET Circuits Against Voltage Over-Scaling.
IEEE Trans. Circuits Syst. I Regul. Pap.
Guilherme Paim, Georgios Zervakis, Girish Pahwa, Yogesh Singh Chauhan, Eduardo Antonio Cesar da Costa, Sergio Bampi, Jörg Henkel, Hussam Amrouch
2021 J jnl
PROTON: Post-Synthesis Ferroelectric Thickness Optimization for NCFET Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sami Salamin, Georgios Zervakis, Yogesh Singh Chauhan, Jörg Henkel, Hussam Amrouch
2021 J jnl
Study of multi-domain switching dynamics in negative capacitance FET using SPICE model.
Microelectron. J.
Amol D. Gaidhane, Amit Verma, Yogesh Singh Chauhan
2021 Misc conf
Transistor Self-Heating: The Rising Challenge for Semiconductor Testing.
VTS
Om Prakash, Chetan K. Dabhi, Yogesh Singh Chauhan, Hussam Amrouch
2020 J jnl
Associative processing using negative capacitance FDSOI transistor for pattern recognition.
Microelectron. J.
Dinesh Rajasekharan, Pragya Kushwaha, Yogesh Singh Chauhan
2020 A conf
Cell Library Characterization using Machine Learning for Design Technology Co-Optimization.
ICCAD
Florian Klemme, Yogesh Singh Chauhan, Jörg Henkel, Hussam Amrouch
2020 — conf
Impact of Radiation on Negative Capacitance FinFET.
IRPS
Govind Bajpai, Aniket Gupta, Om Prakash, Girish Pahwa, Jörg Henkel, Yogesh Singh Chauhan, Hussam Amrouch
2020 J jnl
Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hussam Amrouch, Girish Pahwa, Amol D. Gaidhane, Chetan K. Dabhi, Florian Klemme, Om Prakash, Yogesh Singh Chauhan
2020 — conf
NCFET to Rescue Technology Scaling: Opportunities and Challenges.
ASP-DAC
Hussam Amrouch, Victor M. van Santen, Girish Pahwa, Yogesh Singh Chauhan, Jörg Henkel
2020 J jnl
Power Side-Channel Attacks in Negative Capacitance Transistor (NCFET).
CoRR
Johann Knechtel, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf, Yogesh Singh Chauhan, Jörg Henkel, Ozgur Sinanoglu, Hussam Amrouch
2020 J jnl
Power Side-Channel Attacks in Negative Capacitance Transistor.
IEEE Micro
Johann Knechtel, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf, Yogesh Singh Chauhan, Jörg Henkel, Ozgur Sinanoglu, Hussam Amrouch
2019 — conf
BSIM-BULK: Accurate Compact Model for Analog and RF Circuit Design.
CICC
Chetan Gupta, Ravi Goel, Harshit Agarwal, Chenming Hu, Yogesh Singh Chauhan
2019 A conf
NCFET-Aware Voltage Scaling.
ISLPED
Sami Salamin, Martin Rapp, Hussam Amrouch, Girish Pahwa, Yogesh Singh Chauhan, Jörg Henkel
2019 Misc conf
Neuromorphic Circuits on FDSOI Technology for Computer Vision Applications.
VLSID
Dinesh Rajasekharan, Amit Ranjan Trivedi, Yogesh Singh Chauhan
2019 A* conf
Performance, Power and Cooling Trade-Offs with NCFET-based Many-Cores.
DAC
Martin Rapp, Sami Salamin, Hussam Amrouch, Girish Pahwa, Yogesh Singh Chauhan, Jörg Henkel
2018 J jnl
Negative Capacitance Transistor to Address the Fundamental Limitations in Technology Scaling: Processor Performance.
IEEE Access
Hussam Amrouch, Girish Pahwa, Amol D. Gaidhane, Jörg Henkel, Yogesh Singh Chauhan
2018 — conf
Non-Linear RF Modeling of GaN HEMTs with Industry Standard ASM GaN Model (Invited).
BCICTS
Sourabh Khandelwal, Yogesh Singh Chauhan, Jason Hodges, Sayed Ali Albahrani
2017 Misc conf
Modeling of Body-Bias Dependence of Overlap Capacitances in Bulk MOSFETs.
VLSID
Avirup Dasgupta, Chetan Gupta, Anupam Dutta, Yen-Kai Lin, Srikanth Srihari, Ethirajan Tamilmani, Chenming Hu, Yogesh Singh Chauhan
2016 Misc conf
Analysis of Quantum Capacitance Effect in Ultra-Thin-Body III-V Transistor.
VLSID
Chandan Yadav, Amit Agarwal, Yogesh Singh Chauhan
2016 — conf
Designing energy efficient and hysteresis free negative capacitance FinFET with negative DIBL and 3.5X ION using compact modeling approach.
ESSCIRC
Girish Pahwa, Tapas Dutta, Amit Agarwal, Yogesh Singh Chauhan
2016 J jnl
Thermal resistance modeling in FDSOI transistors with industry standard model BSIM-IMG.
Microelectron. J.
Pragya Kushwaha, K. Bala Krishna, Harshit Agarwal, Sourabh Khandelwal, Juan Pablo Duarte, Chenming Hu, Yogesh Singh Chauhan
2016 Misc conf
Unified Model for Sub-Bandgap and Conventional Impact Ionization in RF SOI MOSFETs with Improved Simulator Convergence.
VLSID
Chandan Yadav, Anupam Dutta, Saurabh Sirohi, Ethirajan Tamilmani, Yogesh Singh Chauhan
2015 — conf
BSIM-CMG: Standard FinFET compact model for advanced circuit design.
ESSCIRC
Juan Pablo Duarte, Sourabh Khandelwal, Aditya Sankar Medury, Chenming Hu, Pragya Kushwaha, Harshit Agarwal, Avirup Dasgupta, Yogesh Singh Chauhan
2015 J jnl
Modeling STI Edge Parasitic Current for Accurate Circuit Simulations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sourabh Khandelwal, Harshit Agarwal, Juan Pablo Duarte, Kaiman Chan, Sagnik Dey, Yogesh Singh Chauhan, Chenming Hu
2014 Misc conf
BSIM6 - Benchmarking the Next-Generation MOSFET Model for RF Applications.
VLSID
Anupam Dutta, Saurabh Sirohi, Ethirajan Tamilmani, Harshit Agarwal, Yogesh Singh Chauhan, Richard Q. Williams
2013 J jnl
BSIM - SPICE Models Enable FinFET and UTB IC Designs.
IEEE Access
Navid Paydavosi, Sriramkumar Venugopalan, Yogesh Singh Chauhan, Juan Pablo Duarte, Srivatsava Jandhyala, Ali M. Niknejad, Chenming Hu
2013 — conf
BSIM compact MOSFET models for SPICE simulation.
MIXDES
Yogesh Singh Chauhan, Sriramkumar Venugopalan, Navid Paydavosi, Pragya Kushwaha, Srivatsava Jandhyala, Juan Pablo Duarte, Shantanu Agnihotri, Chandan Yadav, Harshit Agarwal, Ali Niknejad, Chenming Calvin Hu
2012 — conf
BSIM - Industry standard compact MOSFET models.
ESSCIRC
Yogesh Singh Chauhan, Sriramkumar Venugopalan, Mohammed A. Karim, Sourabh Khandelwal, Navid Paydavosi, Pankaj Thakur, Ali M. Niknejad, Chenming Hu
2012 — conf
Evaluation of the BSIM6 compact MOSFET model's scalability in 40nm CMOS technology.
ESSCIRC
Maria-Anna Chalkiadaki, Anurag Mangla, Christian C. Enz, Yogesh Singh Chauhan, Mohammed Ahosan Ul Karim, Sriramkumar Venugopalan, Ali Niknejad, Chenming Hu
2010 Misc conf
RF SOI Switch FET Design and Modeling Tradeoffs for GSM Applications.
VLSI Design
Shyam Parthasarathy, Amit Ranjan Trivedi, Saurabh Sirohi, Robert A. Groves, Michael Olsen, Yogesh Singh Chauhan, Michael Carroll, Dan Kerr, Ali Tombak, Phil Mason
2008 Misc conf
Compact Modeling of Suspended Gate FET.
VLSI Design
Yogesh Singh Chauhan, Dimitrios Tsamados, Nicolas Abelé, Christoph Eggimann, Michel J. Declercq, Adrian M. Ionescu
2007 Misc conf
A New Charge based Compact Model for Lateral Asymmetric MOSFET and its application to High Voltage MOSFET Modeling.
VLSI Design
Yogesh Singh Chauhan, François Krummenacher, Renaud Gillon, Benoit Bakeroot, Michel J. Declercq, Adrian M. Ionescu
2007 — conf
Suspended-gate FET as a sleep transistor for ultra-low stand-by power applications.
Nano-Net
Dimitrios Tsamados, Yogesh Singh Chauhan, Christoph Eggimann, Adrian Mihai Ionescu
2006 — conf
A Compact DC and AC Model for Circuit Simulation of High Voltage VDMOS Transistor.
ISQED
Yogesh Singh Chauhan, Costin Anghel, François Krummenacher, Renaud Gillon, Andre Baguenier, Bart Desoete, Steven Frere, Adrian Mihai Ionescu, Michel J. Declercq