Yo-Hao Tu

13 papers C 5Journal 5Unranked 3
YearRankTypeTitle / Venue / Authors
2021 J jnl
A Wide-Range All-Digital Delay-Locked Loop for DDR1-DDR5 Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Chih-Wei Tsai, Yu-Ting Chiu, Yo-Hao Tu, Kuo-Hsing Cheng
2019 — conf
A 7.5-mW 10-Gb/s 16-QAM wireline transceiver with carrier synchronization and threshold calibration for mobile inter-chip communications in 16-nm FinFET.
NOCS
Jieqiong Du, Chien-Heng Wong, Yo-Hao Tu, Wei-Han Cho, Yilei Li, Yuan Du, Po-Tsang Huang, Sheau Jiung Lee, Mau-Chung Frank Chang
2018 J jnl
A Power-Saving Adaptive Equalizer With a Digital-Controlled Self-Slope Detection.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yo-Hao Tu, Kuo-Hsing Cheng, Man-Ju Lee, Jen-Chieh Liu
2018 C conf
A Wide-Range All-Digital Delay-Locked Loop for Double Data Rate Synchronous Dynamic Random Access Memory Application.
ISCAS
Chih-Wei Tsai, Yu-Ting Chiu, Yo-Hao Tu, Kuo-Hsing Cheng
2018 J jnl
Low supply voltage and multiphase all-digital crystal-less clock generator.
IET Circuits Devices Syst.
Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Chi-Yang Chang
2017 — conf
A body sensor node SoC for ECG/EMG applications with compressed sensing and wireless powering.
VLSI-DAT
Yo-Hao Tu, Kai-Wen Yao, Minghao Huang, Yu-Yun Lin, Hao-Yu Chi, Po-Min Cheng, Pei-Yun Tsai, Muh-Tian Shiue, Chien-Nan Liu, Kuo-Hsing Cheng, Jia-Shiang Fu
2016 J jnl
A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC.
IEICE Electron. Express
Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Hong-Yi Huang, Chang-Chien Hu
2016 C conf
A chaotically injected timing technique for ring-based oscillators.
DDECS
Yo-Hao Tu, Kuo-Hsing Cheng, Wei-Ren Wang, Jen-Chieh Liu, Hong-Yi Huang
2016 J jnl
Proportional Static-Phase-Error Reduction for Frequency-Multiplier-Based Delay-Locked-Loop Architecture.
IEICE Trans. Electron.
Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng
2015 C conf
A Synchronous Mirror Delay with Duty-Cycle Tunable Technology.
DDECS
Yo-Hao Tu, Kuo-Hsing Cheng, Yian-An Lin, Hong-Yi Huang
2014 C conf
A low supply voltage synchronous mirror delay with quadrature phase output.
DDECS
Yo-Hao Tu, Kuo-Hsing Cheng, Chih-Hsun Hsu, Hong-Yi Huang
2013 C conf
A low jitter delay-locked-loop applied for DDR4.
DDECS
Yo-Hao Tu, Kuo-Hsing Cheng, Hsiang-Yun Wei, Hong-Yi Huang
2010 — conf
A 3 GHz DLL-based clock generator with stuck locking protection.
ICECS
Yo-Hao Tu, Hsiang-Hao Chang, Cheng-Liang Hung, Kuo-Hsing Cheng