Yizhe Hu

25 papers C 2Journal 14Unranked 9
YearRankTypeTitle / Venue / Authors
2026 — conf
34.1 A 128mW 2×4 Radar-on-Chip with Forward-ΔΣ DPLL-Locked Multi-Injection RTWO in 22nm CMOS Enabling ADC-Free Digitization and PS-Free Beamforming Demonstrated in In-Cabin Vital-Sign Monitoring.
ISSCC
Liheng Lou, Zeyu Zhou, Luyao Yuan, Yucheng Long, Gong Chen, Xiaoyu Li, Shaoqi Yang, Han Cui, Ji Peng, Weichen Tao, Juncheng Deng, Yizhe Hu
2026 J jnl
A PLL Technique: Charge-Steering Sampling.
IEEE J. Solid State Circuits
Weichen Tao, Yuhao Yang, Robert Bogdan Staszewski, Yizhe Hu
2025 — conf
A 0.0022 mm
CICC
Tao Lu, Zixiang Liu, Hao Yang, Sai-Weng Sin, Robert Bogdan Staszewski, Fujiang Lin, Liheng Lou, Yizhe Hu
2025 J jnl
A 14-bit 750 MS/s energy-efficient pipelined ADC for MEMS LiDAR system.
Microelectron. J.
Yizhe Hu, Lili Lang, Yemin Dong
2025 J jnl
A 7-Bit 1.41-GS/s 2-Bit/Cycle Precharge-Advancing SAR ADC With Fast Discharge Comparator.
IEEE Trans. Circuits Syst. II Express Briefs
Zixiang Liu, Tao Lu, Sai-Weng Sin, Robert Bogdan Staszewski, Liheng Lou, Yizhe Hu
2025 J jnl
A Charge-Domain Fractional-N ADPLL Based on Charge-Steering Sampling.
IEEE J. Solid State Circuits
Weichen Tao, Yuhao Yang, Weiyi Chen, Robert Bogdan Staszewski, Yizhe Hu
2024 C conf
A 25Gbps Single-Ended to Differential Low-Noise Transimpedance Amplifier in 45nm SOI for High-Speed Optical Transceivers.
TENCON
Juncheng Deng, Luyao Yuan, Zeyu Zhou, JinFeng Xie, Ahmed Wahba, Ping Ma, Yizhe Hu, Fujiang Lin, C. Patrick Yue, Liheng Lou
2023 J jnl
A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain-Gate-Source for Low Flicker Phase Noise and I/Q Exactness.
IEEE J. Solid State Circuits
Xi Chen, Yizhe Hu, Teerachot Siriburanon, Jianglin Du, Robert Bogdan Staszewski, Anding Zhu
2023 — conf
An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and -252 dB FoM.
VLSI Technology and Circuits
Weichen Tao, Weichen Zhao, Robert Bogdan Staszewski, Fujiang Lin, Yizhe Hu
2022 J jnl
A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking.
IEEE J. Solid State Circuits
Yizhe Hu, Xi Chen, Teerachot Siriburanon, Jianglin Du, Vivek Govindaraj, Anding Zhu, Robert Bogdan Staszewski
2022 J jnl
A Compact 0.2-0.3-V Inverse-Class-F
IEEE J. Solid State Circuits
Jianglin Du, Yizhe Hu, Teerachot Siriburanon, Enis Kobal, Philip Quinlan, Anding Zhu, Robert Bogdan Staszewski
2022 J jnl
Flicker Phase-Noise Reduction Using Gate-Drain Phase Shift in Transformer-Based Oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xi Chen, Yizhe Hu, Teerachot Siriburanon, Jianglin Du, Robert Bogdan Staszewski, Anding Zhu
2022 J jnl
Multirate Timestamp Modeling for Ultralow-Jitter Frequency Synthesis: A Tutorial.
IEEE Trans. Circuits Syst. II Express Briefs
Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski
2021 — conf
A 24-31 GHz Reference Oversampling ADPLL Achieving FoMjitter-N of -269.3 dB.
VLSI Circuits
Jianglin Du, Teerachot Siriburanon, Xi Chen, Yizhe Hu, Vivek Govindaraj, Anding Zhu, Robert Bogdan Staszewski
2021 J jnl
A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL.
IEEE J. Solid State Circuits
Jianglin Du, Teerachot Siriburanon, Yizhe Hu, Vivek Govindaraj, Robert Bogdan Staszewski
2021 J jnl
Oscillator Flicker Phase Noise: A Tutorial.
IEEE Trans. Circuits Syst. II Express Briefs
Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski
2020 — conf
17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM.
ISSCC
Yizhe Hu, Xi Chen, Teerachot Siriburanon, Jianglin Du, Zhong Gao, Vivek Govindaraj, Anding Zhu, Robert Bogdan Staszewski
2019 — conf
28 GHz Quadrature Frequency Generation Exploiting Injection-Locked Harmonic Extractors for 5G Communications.
NEWCAS
Zhong Gao, Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski
2019 — conf
A 0.3V, 35% Tuning-Range, 60kHz 1/f
CICC
Jianglin Du, Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski
2019 — conf
DTC-Assisted All-Digital Phase-Locked Loop Exploiting Hybrid Time/Voltage Phase Digitization.
APCCAS
Vivek Govindaraj, Jianglin Du, Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski
2019 J jnl
Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs
Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski
2018 J jnl
A Low-Flicker-Noise 30-GHz Class-F
IEEE J. Solid State Circuits
Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski
2017 — conf
A 30-GHz class-F23 oscillator in 28nm CMOS using harmonic extraction and achieving 120 kHz 1/f
ESSCIRC
Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski
2015 C conf
A modeling approach for mixed-mode FMCW synthesizer allowing frequency error analysis.
ISCAS
Yizhe Hu, Wei Li
2013 J jnl
A Low Power and variation-Insensitive Current-Mode Signaling Scheme.
J. Circuits Syst. Comput.
Xinsheng Wang, Yizhe Hu, Liang Han, Jinghu Li, Chenxu Wang, Mingyan Yu