Yitao Ma

15 papers C 1Journal 11Unranked 3
YearRankTypeTitle / Venue / Authors
2023 J jnl
Corrections to "Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator".
IEEE Trans. Very Large Scale Integr. Syst.
Tao Li, Yitao Ma, Ko Yoshikawa, Tetsuo Endoh
2023 J jnl
From Algorithm to Module: Adaptive and Energy-Efficient Quantization Method for Edge Artificial Intelligence in IoT Society.
IEEE Trans. Ind. Informatics
Tao Li, Yitao Ma, Tetsuo Endoh
2023 J jnl
Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator.
IEEE Trans. Very Large Scale Integr. Syst.
Tao Li, Yitao Ma, Ko Yoshikawa, Tetsuo Endoh
2023 J jnl
Neuromorphic processor-oriented hybrid Q-format multiplication with adaptive quantization for tiny YOLO3.
Neural Comput. Appl.
Tao Li, Yitao Ma, Tetsuo Endoh
2022 J jnl
Energy-Efficient Convolution Module With Flexible Bit-Adjustment Method and ADC Multiplier Architecture for Industrial IoT.
IEEE Trans. Ind. Informatics
Tao Li, Yitao Ma, Ko Yoshikawa, Osamu Nomura, Tetsuo Endoh
2021 J jnl
Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition.
IEEE J. Solid State Circuits
Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
2020 J jnl
A Systematic Study of Tiny YOLO3 Inference: Toward Compact Brainware Processor With Less Memory and Logic Gate.
IEEE Access
Tao Li, Yitao Ma, Tetsuo Endoh
2020 — conf
Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage.
VLSI Circuits
Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
2020 J jnl
FPGA Implementation of Real-Time Pedestrian Detection Using Normalization-Based Validation of Adaptive Features Clustering.
IEEE Trans. Veh. Technol.
Tao Li, Yitao Ma, Hui Shen, Tetsuo Endoh
2020 J jnl
Normalization-Based Validity Index of Adaptive K-Means Clustering for Multi-Solution Application.
IEEE Access
Tao Li, Yitao Ma, Tetsuo Endoh
2019 J jnl
A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications.
IEEE J. Solid State Circuits
Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
2019 — conf
An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz.
ISSCC
Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
2016 J jnl
Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing.
Proc. IEEE
Takahiro Hanyu, Tetsuo Endoh, Daisuke Suzuki, Hiroki Koike, Yitao Ma, Naoya Onizawa, Masanori Natsui, Shoji Ikeda, Hideo Ohno
2013 C conf
An MTJ-based nonvolatile associative memory architecture with intelligent power-saving scheme for high-speed low-power recognition applications.
ISCAS
Yitao Ma, Tadashi Shibata, Tetsuo Endoh
2011 — conf
A vertical-MOSFET-based digital core circuit for high-speed low-power vector matching.
ISOCC
Yitao Ma, Tetsuo Endoh, Tadashi Shibata