Yishuang Lin - RankMe

11 papers A 3Journal 2Unranked 6

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yishuang Lin, Yaguang Li, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2023	—	`conf`	Fully Automated Machine Learning Model Development for Analog Placement Quality Prediction. ASP-DAC Chen-Chia Chang, Jingyu Pan, Zhiyao Xie, Yaguang Li, Yishuang Lin, Jiang Hu, Yiran Chen
2023	—	`conf`	MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs. MLCAD Yishuang Lin, Yaguang Li, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2023	J	`jnl`	Performance-driven Wire Sizing for Analog Integrated Circuits. ACM Trans. Design Autom. Electr. Syst. Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2022	A	`conf`	Are Analytical Techniques Worthwhile for Analog IC Placement? DATE Yishuang Lin, Yaguang Li, Donghao Fang, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2022	—	`conf`	Mapping Large Scale Finite Element Computing on to Wafer-Scale Engines. ASP-DAC Yishuang Lin, Rongjian Liang, Yaguang Li, Hailiang Hu, Jiang Hu
2021	—	`conf`	A Circuit Attention Network-Based Actor-Critic Learning Approach to Robust Analog Transistor Sizing. MLCAD Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2021	—	`conf`	Machine Learning Techniques in Analog Layout Automation. ISPD Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
2020	A	`conf`	A Customized Graph Neural Network Model for Guiding Analog IC Placement. ICCAD Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2020	—	`conf`	Exploring a Machine Learning Approach to Performance Driven Analog IC Placement. ISVLSI Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2020	A	`conf`	The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). ICCAD Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar