Yiqiang Ding - RankMe

20 papers C 3Journal 11Unranked 6

Year	Rank	Type	Title / Venue / Authors
2015	J	`jnl`	Exploiting Static Non-Uniform Cache Architectures for Hard Real-Time Computing. J. Comput. Sci. Eng. Yiqiang Ding, Wei Zhang
2014	—	`conf`	Bounding the Worst-Case Execution Time of Static NUCA Caches. HPCC/CSS/ICESS Yiqiang Ding, Wei Zhang
2014	—	`conf`	Characterizing Energy Consumption of Real-Time and Media Benchmarks on Hybrid SPM-Caches. HPCC/CSS/ICESS Lan Wu, Yiqiang Ding, Wei Zhang
2014	J	`jnl`	Comparing Separate and Statically-Partitioned Caches for Time-Predictable Multicore Processors. J. Comput. Sci. Eng. Lan Wu, Yiqiang Ding, Wei Zhang
2014	J	`jnl`	Exploiting Standard Deviation of CPI to Evaluate Architectural Time-Predictability. J. Comput. Sci. Eng. Wei Zhang, Yiqiang Ding
2014	C	`conf`	Hop-Based Priority Scheduling to Improve Worst-Case Inter-core Communication Latency. EUC Yiqiang Ding, Wei Zhang
2014	C	`conf`	WCET analysis of static NUCA caches. IPCCC Yiqiang Ding, Wei Zhang
2013	J	`jnl`	Bounding Worst-Case DRAM Performance on Multicore Processors. J. Comput. Sci. Eng. Yiqiang Ding, Lan Wu, Wei Zhang
2013	J	`jnl`	Counter-Based Approaches for Efficient WCET Analysis of Multicore Processors with Shared Caches. J. Comput. Sci. Eng. Yiqiang Ding, Wei Zhang
2013	—	`conf`	Hybrid SPM-cache architectures to achieve high time predictability and performance. ASAP Wei Zhang, Yiqiang Ding
2013	J	`jnl`	Multicore Real-Time Scheduling to Reduce Inter-Thread Cache Interferences. J. Comput. Sci. Eng. Yiqiang Ding, Wei Zhang
2013	—	`conf`	On the interactions between real-time scheduling and inter-thread cached interferences for multicore processors. ISQED Yiqiang Ding, Wei Zhang
2013	—	`conf`	Standard deviation of CPI: A new metric to evaluate architectural time predictability. ASAP Wei Zhang, Yiqiang Ding
2012	J	`jnl`	Architectural time-predictability factor (ATF): a metric to evaluate time predictability of processors. SIGBED Rev. Yiqiang Ding, Wei Zhang
2012	J	`jnl`	Multicore-Aware Code Co-Positioning to Reduce WCET on Dual-Core Processors with Shared Instruction Caches. J. Comput. Sci. Eng. Yiqiang Ding, Wei Zhang
2011	C	`conf`	Multicore-Aware Code Positioning to Improve Worst-Case Performance. ISORC Yiqiang Ding, Wei Zhang
2010	—	`conf`	Improving the static real-time scheduling on multicore processors by reducing worst-case inter-thread cache interferences. ACM Southeast Regional Conference Yiqiang Ding, Wei Zhang
2010	J	`jnl`	Loop-Based Instruction Prefetching to Reduce the Worst-Case Execution Time. IEEE Trans. Computers Yiqiang Ding, Wei Zhang
2009	J	`jnl`	Optimizing Instruction Prefetching to Improve Worst-Case Performance for Real-Time Applications. J. Comput. Sci. Eng. Yiqiang Ding, Jun Yan, Wei Zhang
1999	J	`jnl`	An improvement of GNY logic for the reflection attacks. J. Comput. Sci. Technol. Yiqiang Ding