Yiorgos Tsiatouhas

75 papers A 4B 7C 12Misc 1Journal 19Unranked 32

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	BTI Aging Analysis and Mitigation for Differential Input In-Memory Computing SRAMs. IEEE Trans. Very Large Scale Integr. Syst. Christina Dilopoulou, Yiorgos Tsiatouhas
2025	A	`conf`	CAS-PUF: Current-Mode Array-Type Strong PUF for Secure Computing in Area Constrained SoCs. DATE Dimosthenis Georgoulas, Yiorgos Tsiatouhas, Vasileios Tenentes
2025	—	`conf`	Efficient Tree Architecture for the Design of Static CMOS Magnitude Comparators. ISVLSI Constantinos Efstathiou, John Liaperdos, Yiorgos Tsiatouhas
2024	—	`conf`	Deep Learning Based Detection of Anti-Reflective Obstacles in VLC Systems. ICAIIC Marina E. Plissiti, Christoforos Papaioannou, Yiorgos Sfikas, Georgios Papatheodorou, Simon-Ilias Poulis, Aristides Efthymiou, Yiorgos Tsiatouhas
2024	A	`conf`	Testing Algorithms for Hard to Detect Thermal Crosstalk Induced Write Disturb Faults in Phase Change Memories. DATE Spyridon Spyridonos, Yiorgos Tsiatouhas
2023	J	`jnl`	An aging monitoring scheme for SRAM decoders. Integr. Helen-Maria Dounavi, Yiorgos Tsiatouhas
2023	—	`conf`	BTI Aging Influence and Mitigation in Neural Networks Oriented In-Memory Computing SRAMs. MOCAST Christina Dilopoulou, Yiorgos Tsiatouhas
2023	—	`conf`	BTI Aging Influence in SRAM-based In-Memory Computing Schemes and its Mitigation. ICECS Christina Dilopoulou, Yiorgos Tsiatouhas
2023	—	`conf`	Embedded Platforms for Trusted Edge Computing Towards Quality Assurance Along the Supply Chain. SEEDA-CECNSM Vasileios Tenentes, Athanasios Xynos, Christos Zonios, Asimina Koutra, Christina Dilopoulou, Konstantinos Tsampiras, Yiorgos Tsiatouhas, Daniele Rossi
2023	B	`conf`	SiCBit-PUF: Strong in-Cache Bitflip PUF Computation for Trusted SoCs. ETS Athanasios Xynos, Vasileios Tenentes, Yiorgos Tsiatouhas
2022	—	`conf`	BTI Aging Influence on Charge Pump Circuits. MOCAST Spyridon Spyridonos, Yiorgos Tsiatouhas
2022	C	`conf`	Efficient Dynamic Logic Magnitude Comparators. VLSI-SoC Constantinos Efstathiou, Laura Agalioti, Yiorgos Tsiatouhas
2022	—	`conf`	Signal decoding in an NLOS VLC system with the presence of anti-reflective obstacles. BlackSeaCom Christoforos Papaioannou, Marina E. Plissiti, Yiorgos Sfikas, Georgios Papatheodorou, Simon-Ilias Poulis, Aristides Efthymiou, Yiorgos Tsiatouhas
2021	J	`jnl`	A Low-Cost, Robust and Tolerant, Digital Scheme for Post-Bond Testing and Diagnosis of TSVs. J. Electron. Test. Vasileios Gerakis, Yiorgos Tsiatouhas, Alkis A. Hatzopoulos
2021	J	`jnl`	Aging Prediction and Tolerance for the SRAM Memory Cell and Sense Amplifier. J. Electron. Test. Helen-Maria Dounavi, Yiorgos Sfikas, Yiorgos Tsiatouhas
2021	—	`conf`	An efficient adaptive thresholding scheme for signal decoding in NLOS VLC systems. MeditCom Marina E. Plissiti, Christoforos Papaioannou, Yiorgos Sfikas, Georgios Papatheodorou, Simon-Ilias Poulis, Aristides Efthymiou, Yiorgos Tsiatouhas
2020	—	`conf`	An Alternative Post-bond Testing Method for TSVs. MOCAST Vasileios Gerakis, Yiorgos Tsiatouhas, Alkis A. Hatzopoulos
2020	B	`conf`	Monitoring of BTI and HCI Aging in SRAM Decoders. ETS Helen-Maria Dounavi, Yiorgos Tsiatouhas
2019	—	`conf`	On the Static CMOS Implementation of Magnitude Comparators. PATMOS Costas Efstathiou, Yiorgos Tsiatouhas
2018	—	`conf`	Aging monitoring in SRAM sense amplifiers. MOCAST Helen-Maria Dounavi, Yiorgos Sfikas, Yiorgos Tsiatouhas
2018	—	`conf`	Low Power and High Speed Static CMOS Digital Magnitude Comparators. ICECS Costas Efstathiou, K. Dimolikas, Christoforos Papaioannou, Yiorgos Tsiatouhas
2018	C	`conf`	Periodic Aging Monitoring in SRAM Sense Amplifiers. IOLTS Helen-Maria Dounavi, Yiorgos Sfikas, Yiorgos Tsiatouhas
2017	—	`conf`	BTI and HCI degradation detection in SRAM cells. MOCAST Yiorgos Sfikas, Yiorgos Tsiatouhas
2017	—	`conf`	Oscillation-based technique for post-bond parallel testing and diagnosis of multiple TSVs. PATMOS Stylianos-Georgios Papadopoulos, Vasileios Gerakis, Yiorgos Tsiatouhas, Alkis A. Hatzopoulos
2017	B	`conf`	Periodic Bias-Temperature Instability monitoring in SRAM cells. ETS Yiorgos Tsiatouhas
2017	C	`conf`	Variation tolerant BTI monitoring in SRAM cells. IOLTS Yiorgos Sfikas, Yiorgos Tsiatouhas
2016	—	`conf`	Low-Power and High Performance Sinusoidal Clocked Dynamic Circuit Design. ISVLSI Raghava Katreepalli, Hemanth Chemanchula, Themistoklis Haniotakis, Yiorgos Tsiatouhas
2016	J	`jnl`	Testing Neighbouring Cell Leakage and Transition Induced Faults in DRAMs. IEEE Trans. Computers Yiorgos Sfikas, Yiorgos Tsiatouhas
2016	J	`jnl`	Timing Error Tolerance in Small Core Designs for SoC Applications. IEEE Trans. Computers Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni
2016	—	`conf`	Timing error mitigation in microprocessor cores. ICECS Stefanos Valadimas, Angela Arapoyanni, Yiorgos Tsiatouhas
2015	J	`jnl`	A current monitoring technique for I Integr. Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
2015	A	`conf`	A method for the estimation of defect detection probability of analog/RF defect-oriented tests. DATE John Liaperdos, Angela Arapoyanni, Yiorgos Tsiatouhas
2015	A	`conf`	Fast deployment of alternate analog test using Bayesian model fusion. DATE John Liaperdos, Haralampos-G. D. Stratigopoulos, Louay Abdallah, Yiorgos Tsiatouhas, Angela Arapoyanni, Xin Li
2015	B	`conf`	On resistive open defect detection in DRAMs: The charge accumulation effect. ETS Yiorgos Sfikas, Yiorgos Tsiatouhas, Mottaqiallah Taouil, Said Hamdioui
2015	C	`conf`	On the reuse of existing error tolerance circuitry for low power scan testing. ISCAS Anthi Anastasiou, Yiorgos Tsiatouhas, Angela Arapoyanni
2015	—	`conf`	Scan chain based at-speed diagnosis in the presence of scan output compaction schemes. Panhellenic Conference on Informatics Helen-Maria Dounavi, Yiorgos Tsiatouhas, Angela Arapoyanni
2015	C	`conf`	Soft error immune latch under SEU related double-node charge collection. IOLTS Katerina Katsarou, Yiorgos Tsiatouhas
2014	J	`jnl`	Built-In Self-Test, Diagnosis, and Repair of MultiMode Power Switches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ran Wang, Zhaobo Zhang, Xrysovalantis Kavousianos, Yiorgos Tsiatouhas, Krishnendu Chakrabarty
2014	C	`conf`	Double node charge sharing SEU tolerant latch design. IOLTS Katerina Katsarou, Yiorgos Tsiatouhas
2014	J	`jnl`	Layout-Based Refined NPSF Model for DRAM Characterization and Testing. IEEE Trans. Very Large Scale Integr. Syst. Yiorgos Sfikas, Yiorgos Tsiatouhas, Said Hamdioui
2014	J	`jnl`	Low-Power Scan Testing: A Scan Chain Partitioning and Scan Hold Based Technique. J. Electron. Test. Efi Arvaniti, Yiorgos Tsiatouhas
2014	B	`conf`	Power efficient scan testing by exploiting existing error tolerance circuitry in a design. ETS Anthi Anastasiou, Yiorgos Tsiatouhas
2014	J	`jnl`	Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches. IEEE Trans. Very Large Scale Integr. Syst. Zhaobo Zhang, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Yiorgos Tsiatouhas
2014	—	`conf`	Stuck-at fault diagnosis in scan chains. DTIS Helen-Maria Dounavi, Yiorgos Tsiatouhas
2014	J	`jnl`	The Time Dilation Technique for Timing Error Tolerance. IEEE Trans. Computers Stefanos Valadimas, Andreas Floros, Yiorgos Tsiatouhas, Angela Arapoyanni, Xrysovalantis Kavousianos
2013	J	`jnl`	A Built-In Voltage Measurement Technique for the Calibration of RF Mixers. IEEE Trans. Instrum. Meas. John Liaperdos, Angela Arapoyanni, Yiorgos Tsiatouhas
2013	J	`jnl`	Effective Timing Error Tolerance in Flip-Flop Based Core Designs. J. Electron. Test. Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni, Petros Xarchakos
2013	C	`conf`	NBTI aging tolerance in pipeline based designs NBTI. IOLTS Katerina Katsarou, Yiorgos Tsiatouhas, Angela Arapoyanni
2013	J	`jnl`	New High-Speed Multioutput Carry Look-Ahead Adders. IEEE Trans. Circuits Syst. II Express Briefs Costas Efstathiou, Zaher Owda, Yiorgos Tsiatouhas
2012	—	`conf`	A novel architecture to reduce test time in march-based SRAM tests. DTIS Ioannis Voyiatzis, Costas Efstathiou, Yiorgos Tsiatouhas, Cleo Sgouropoulou
2012	B	`conf`	Cost and power efficient timing error tolerance in flip-flop based microprocessor cores. ETS Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni
2012	C	`conf`	Low power scan by partitioning and scan hold. DDECS Efi Arvaniti, Yiorgos Tsiatouhas
2012	—	`conf`	Single event upset tolerance in flip-flop based microprocessor cores. DFT Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni, Adrian Evans
2012	—	`conf`	Testing wireless transceivers' RF front-ends utilizing defect-oriented BIST techniques. ICECS Lampros Dermentzoglou, John Liaperdos, Angela Arapoyanni, Yiorgos Tsiatouhas
2012	—	`conf`	The leafs scan-chain for test application time and scan power reduction. ICECS Maria Chalkia, Yiorgos Tsiatouhas
2011	C	`conf`	A BIST scheme for testing and repair of multi-mode power switches. IOLTS Zhaobo Zhang, Xrysovalantis Kavousianos, Yiorgos Tsiatouhas, Krishnendu Chakrabarty
2011	Misc	`conf`	A Robust and Reconfigurable Multi-mode Power Gating Architecture. VLSI Design Zhaobo Zhang, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Yiorgos Tsiatouhas
2011	B	`conf`	Signature Analysis for Testing, Diagnosis, and Repair of Multi-mode Power Switches. ETS Zhaobo Zhang, Xrysovalantis Kavousianos, Yan Luo, Yiorgos Tsiatouhas, Krishnendu Chakrabarty
2010	C	`conf`	A Build-In Self-Test technique for RF Mixers. DDECS Lambros Dermentzoglou, Angela Arapoyanni, Yiorgos Tsiatouhas
2010	J	`jnl`	A Built-In-Test Circuit for RF Differential Low Noise Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. Lambros Dermentzoglou, Angela Arapoyanni, Yiorgos Tsiatouhas
2010	—	`conf`	A Receiver Circuit for Low-Swing Interconnect Schemes. ISVLSI Yiannis Moisiadis, Yiorgos Tsiatouhas
2010	—	`conf`	Memory-Less Pipeline Dynamic Circuit Design Technique. ISVLSI Themistoklis Haniotakis, Zaher Owda, Yiorgos Tsiatouhas
2010	C	`conf`	Timing error tolerance in nanometer ICs. IOLTS Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni
2009	C	`conf`	Physical design oriented DRAM Neighborhood Pattern Sensitive Fault testing. DDECS Yiorgos Sfikas, Yiorgos Tsiatouhas
2008	J	`jnl`	A Current Mode, Parallel, Two-Rail Code Checker. IEEE Trans. Computers Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni
2008	—	`conf`	Timing Error Detection and Correction by Time Dilation. VLSI-SoC (Selected Papers) Andreas Floros, Yiorgos Tsiatouhas, Xrysovalantis Kavousianos
2007	—	`conf`	A Scan Flip-Flop for Low-Power Scan Operation. ICECS Yiorgos Tsiatouhas, Angela Arapoyanni, Dionisis Skias
2007	J	`jnl`	A Stress-Relaxed Negative Voltage-Level Converter. IEEE Trans. Circuits Syst. II Express Briefs Yiorgos Tsiatouhas
2007	—	`conf`	An Embedded Test Circuit for RF Single Ended Low Noise Amplifiers. ICECS Lampros Dermentzoglou, Anastasios Karagounis, Aggeliki Arapoyanni, Yiorgos Tsiatouhas
2006	J	`jnl`	A Design Technique for Energy Reduction in NORA CMOS Logic. IEEE Trans. Circuits Syst. I Regul. Pap. Konstantinos Limniotis, Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni
2006	—	`conf`	A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism. ICECS Andreas Floros, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
2005	—	`conf`	A built-in I ESSCIRC Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Th. Haniotakis, Guillaume Prenat, Salvador Mir
2005	—	`conf`	An embedded IDDQ testing circuit and technique. ICECS Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
2003	—	`conf`	A low power NORA circuit design technique based on charge recycling. ICECS Yiorgos Tsiatouhas, Konstantinos Limniotis, Angela Arapoyanni, Themistoklis Haniotakis
2003	—	`conf`	A novel scheme for testing radio frequency voltage controlled oscillators. ICECS Lampros Dermentzoglou, Yiorgos Tsiatouhas, Angela Arapoyanni