Yinyin Lin - RankMe

40 papers A* 1A 1C 7Journal 20Unranked 11

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	DeepPiC: xPU-PIM Cluster Architecture with Adaptive Resource-Aware Task Orchestration for DeepSeek-Style MoE Inference. ASP-DAC Zixu Li, Manni Li, Zijian Huang, Jiayu Yang, Wending Zhao, Yinyin Lin, Chengchen Wang, Haidong Tian, Xiankui Xiong
2025	J	`jnl`	A 0.09-pJ/Bit Logic-Compatible Multiple-Time Programmable (MTP) Memory-Based PUF Design for IoT Applications. IEEE Trans. Very Large Scale Integr. Syst. Shuming Guo, Yinyin Lin, Hao Wang, Yao Li, Chongyan Gu, Weiqiang Liu, Yijun Cui
2025	C	`conf`	APCPU: Adaptive-Pooling Compression Processing Unit for Energy-Efficient DNNs Processing. ISCAS Wang Wang, Wending Zhao, Manni Li, Zixu Li, Jiayu Yang, Zijian Huang, Yinyin Lin, Chengchen Wang, Xiankui Xiong
2025	C	`conf`	CPSnB: Compressing and Processing Spatial Similarity near Memory Bank for DNNs. ISCAS Wang Wang, Xin Zhong, Manni Li, Zixu Li, Jiayu Yang, Zijian Huang, Yinyin Lin, Chengchen Wang, Xiankui Xiong
2025	—	`conf`	Digital Predistortion for Quadrature Digital Power Amplifiers Using Deep Neural Network of AT_LSTM: Attention LSTM. ACM Great Lakes Symposium on VLSI Jiayu Yang, Wending Zhao, Yicheng Li, Wang Wang, Zixu Li, Manni Li, Zijian Huang, Yinyin Lin, Yun Yin, Hongtao Xu
2025	J	`jnl`	Digital Predistortion for Wide Dynamic Power Range Quadrature Switched-Capacitor Power Amplifiers Using Self-Adaptive Residual LSTM Neural Network. IEEE Trans. Very Large Scale Integr. Syst. Jiayu Yang, Luyi Guo, Yicheng Li, Yinyin Lin, Yun Yin, Hongtao Xu
2025	J	`jnl`	Digital Predistortion of Quadrature Digital Power Amplifiers Using RVRTCNN: Real-Valued Residual Temporal Convolutional Neural Network. IEEE Commun. Lett. Jiayu Yang, Wending Zhao, Yicheng Li, Wang Wang, Zixu Li, Manni Li, Zijian Huang, Yinyin Lin, Yun Yin, Hongtao Xu
2025	J	`jnl`	GPOS: A General and Precise Offloading Strategy for High Generality of DNN Acceleration by OCP and NDP Co-Optimizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zixu Li, Wang Wang, Manni Li, Jiayu Yang, Zijian Huang, Xin Zhong, Yinyin Lin, Chengchen Wang, Xiankui Xiong
2025	A	`conf`	Linearization of Quadrature Digital Power Amplifiers by Neural Network of ULR_LSTM: Unsupervised Learning Residual LSTM. DATE Jiayu Yang, Luyi Guo, Yicheng Li, Wang Wang, Zixu Li, Manni Li, Zijian Huang, Yinyin Lin, Yun Yin, Hongtao Xu
2025	A*	`conf`	Unmask Tampering: Efficient Document Tampering Localization under Recapturing Attacks with Real Distortion Knowledge. CCS Changsheng Chen, Wenyu Chen, Yinyin Lin, Bin Li, Jiwu Huang
2024	C	`conf`	LauWS: Local Adaptive Unstructured Weight Sparsity of Load Balance for DNN in Near-Data Processing. ISCAS Zixu Li, Wang Wang, Xin Zhong, Manni Li, Jiayu Yang, Yinyin Lin, Guhyun Kim, Yosub Song, Chengchen Wang, Xiankui Xiong
2023	J	`jnl`	ANS: Assimilating Near Similarity at High Accuracy for Significant Deduction of CNN Storage and Computation. IEEE Access Wang Wang, Xin Zhong, Manni Li, Zixu Li, Yinyin Lin
2022	J	`jnl`	Statistical Observations of Three Co-Existing NBTI Behaviors in 28 nm HKMG by On-Chip Monitor With Less Recovery Impact. IEEE Trans. Circuits Syst. I Regul. Pap. Yarong Fu, Wang Wang, Xin Zhong, Manni Li, Zixu Li, Qing Dong, Yu Jiang, Yinyin Lin
2017	J	`jnl`	3D domain wall memory-cell structure, array architecture and operation algorithm with anti-disturbance. Microelectron. J. Yarong Fu, Kai Yang, B. A. Chen, Yinyin Lin
2017	C	`conf`	A small area and low power true random number generator using write speed variation of oxidebased RRAM for IoT security application. ISCAS Jianguo Yang, Yinyin Lin, Yarong Fu, Xiaoyong Xue, B. A. Chen
2017	J	`jnl`	Dynamic Data-Dependent Reference to Improve Sense Margin and Speed of Magnetoresistive Random Access Memory. IEEE Trans. Circuits Syst. II Express Briefs Xiaoyong Xue, Yarong Fu, Yanqing Zhao, Juan Xu, Jianguo Yang, Yufeng Xie, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu
2017	—	`conf`	ReRAM write circuit with dynamic uniform and small overshoot compliance current under PVT variations. ASICON Yun Yin, Junlin Gou, Junyi Wang, Yarong Fu, Xiaoyong Xue, Yinyin Lin
2017	J	`jnl`	Retention-Aware Hybrid Main Memory (RAHMM): Big DRAM and Little SCM. IEEE Trans. Computers Weiliang Jing, Kai Yang, Yinyin Lin, Beomseop Lee, Sangkyu Yoon, Yong Ye, Yuan Du, Bomy Chen
2016	J	`jnl`	A Logic Resistive Memory Chip for Embedded Key Storage With Physical Security. IEEE Trans. Circuits Syst. II Express Briefs Yufeng Xie, Xiaoyong Xue, Jianguo Yang, Yinyin Lin, Qingtian Zou, Ryan Huang, Jingang Wu
2016	C	`conf`	A compact pico-second in-situ sensor using programmable ring oscillators for advanced on chip variation characterization in 28nm HKMG. ISCAS Yinyin Lin, Xinyi Hu, Jianguo Yang, Xiaoyong Xue
2016	J	`jnl`	A self-adaptive write driver with fast termination of step-up pulse for ReRAM. IEICE Electron. Express Jianguo Yang, Xiaoyong Xue, Juan Xu, Fan Ye, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu
2016	J	`jnl`	Low-Power Variation-Tolerant Nonvolatile Lookup Table Design. IEEE Trans. Very Large Scale Integr. Syst. Xiaoyong Xue, Jianguo Yang, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu
2016	C	`conf`	Novel 3D horizontal RRAM architecture with isolation cell structure for sneak current depression. ISCAS Yanqing Zhao, Juan Xu, Jianguo Yang, Xiaoyong Xue, Yinyin Lin, Jaehwang Sim
2015	C	`conf`	3D vertical RRAM architecture and operation algorithms with effective IR-drop suppressing and anti-disturbance. ISCAS Yinyin Lin, Rui Yuan, Xiaoyong Xue, B. A. Chen
2015	—	`conf`	A low cost and high reliability true random number generator based on resistive random access memory. ASICON Jianguo Yang, Juan Xu, Bo Wang, Xiaoyong Xue, Ryan Huang, Qingtian Zou, Jingang Wu, Yinyin Lin
2015	—	`conf`	Impacts of external magnetic field and high temperature disturbance on MRAM reliability based on FPGA test platform. ASICON Kai Yang, Yanqing Zhao, Jianguo Yang, Xiaoyong Xue, Yinyin Lin, Jun-Soo Bae
2013	J	`jnl`	A 0.13 µm 8 Mb Logic-Based Cu IEEE J. Solid State Circuits Xiaoyong Xue, Wenxiang Jian, Jianguo Yang, Fanjie Xiao, Gang Chen, Shuliu Xu, Yufeng Xie, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu
2013	—	`conf`	A 2Mb ReRAM with two bits error correction codes circuit for high reliability application. ASICON Jianguo Yang, Ying Meng, Xiaoyong Xue, Ryan Huang, Q. T. Zhou, J. G. Wu, Yinyin Lin
2013	—	`conf`	Low-power high-yield SRAM design with VSS adaptive boosting and BL capacitance variation sensing. ASICON Ningxi Liu, Yu Jiang, Qing Dong, Hui Li, Xinyi Hu, Yinyin Lin
2013	—	`conf`	Novel operation scheme and technological optimization for 1T bulk capacitor-less DRAM. ASICON Hui Li, Wei Zhu, Ningxi Liu, Cunlin Dong, Chao Meng, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu
2012	J	`jnl`	64Kb logic RRAM chip resisting physical and side-channel attacks for encryption keys storage. IEICE Electron. Express Yufeng Xie, Wenxiang Jian, Xiaoyong Xue, Gang Jin, Yinyin Lin
2012	—	`conf`	A 0.13µm 8Mb logic based CuxSiyO resistive memory with self-adaptive yield enhancement and operation power reduction. VLSIC Xiaoyong Xue, W. X. Jian, Jianguo Yang, F. J. Xiao, G. Chen, X. L. Xu, Y. F. Xie, Yinyin Lin, R. Huang, Q. T. Zhou, J. G. Wu
2012	J	`jnl`	Variation-tolerant Cu IEICE Electron. Express Wenxiang Jian, Gang Jin, Na Yan, Zhongyu Bi, Hao Min, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu
2011	—	`conf`	A BIST scheme for high-speed Gain Cell eDRAM. ASICON Bing Yan, Yufeng Xie, Rui Yuan, Yinyin Lin
2011	J	`jnl`	Novel 2T programmable element to improve density and performance of FPGA. IEICE Electron. Express Xiaoyong Xue, Yufeng Xie, Yinyin Lin
2011	—	`conf`	Novel RRAM programming technology for instant-on and high-security FPGAs. ASICON Xiaoyong Xue, Wenxiang Jian, Yufeng Xie, Qing Dong, Rui Yuan, Yinyin Lin
2010	J	`jnl`	A 3D RRAM Using a Stackable Multi-Layer 1TXR Cell. IEICE Trans. Electron. Ji Zhang, Yiqing Ding, Xiaoyong Xue, Gang Jin, Yuxin Wu, Yufeng Xie, Yinyin Lin
2007	J	`jnl`	Multilevel Storage in Phase-Change Memory. IEICE Trans. Electron. Yang Hong, Yinyin Lin, Tingao Tang, Bomy Chen
2006	J	`jnl`	Characterization of Ge Microelectron. J. Feifei Liao, Yiqing Ding, Yinyin Lin, Tingao Tang, Baowei Qiao, Yunfeng Lai, Jie Feng, Bomy Chen
2006	J	`jnl`	Electronic properties of GST for non-volatile memory. Microelectron. J. Hangbing Lv, Peng Zhou, Yinyin Lin, Tingao Tang, Baowei Qiao, Yunfeng Lai, Jie Feng, Bingchu Cai, Bomy Chen