Yinhe Han

287 papers A* 43A 30B 4C 15Misc 1Journal 131Unranked 63
YearRankTypeTitle / Venue / Authors
2026 J jnl
A System Architecture for Low Latency Multiprogramming Quantum Computing.
CoRR
Yilun Zhao, Yu Chen, Kaiyan Chang, He Li, Bing Li, Yinhe Han, Ying Wang
2026 J jnl
CGR-NPU: A Hybrid CGRA and NPU Architecture for Adaptive Neural Computing Workloads.
IEEE Comput. Archit. Lett.
Junzhe Jing, Feng Min, Yiming Gan, Ying Wang, Yinhe Han
2026 J jnl
Chipletizer 2.0: Toward Cost-Effective Chiplet Design via Reuse-Aware Decomposition.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Fuping Li, Ding Yuan, Yujie Wang, Juelei Zhou, Xihao Liang, Yinhe Han, Huawei Li, Xiaowei Li, Ying Wang
2026 J jnl
Chiplever: A Hardware-Software Co-Design Framework Toward Extension of Chiplet System for Fully Homomorphic Encryption.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yibo Du, Ying Wang, Mengdi Wang, Xiaowei Li, Yinhe Han
2026 J jnl
From Buffers to Registers: Unlocking Fine-Grained FlashAttention with Hybrid-Bonded 3D NPU Co-Design.
CoRR
Jinxin Yu, Yudong Pan, Mengdi Wang, Huawei Li, Yinhe Han, Xiaowei Li, Ying Wang
2026 — conf
I/O Analysis is All You Need: An I/O Analysis for Long-Sequence Attention.
ASPLOS (2)
Xiaoyang Lu, Boyu Long, Xiaoming Chen, Yinhe Han, Xian-He Sun
2026 — conf
Ouroboros: Wafer-Scale SRAM CIM with Token-Grained Pipelining for Large Language Model Inference.
ASPLOS (2)
Yiqi Liu, Yudong Pan, Mengdi Wang, Shixin Zhao, Haonan Zhu, Yinhe Han, Lei Zhang, Ying Wang
2026 J jnl
Ouroboros: Wafer-Scale SRAM CIM with Token-Grained Pipelining for Large Language Model Inference.
CoRR
Yiqi Liu, Yudong Pan, Mengdi Wang, Shixin Zhao, Haonan Zhu, Yinhe Han, Lei Zhang, Ying Wang
2026 J jnl
PAM: Processing Across Memory Hierarchy for Efficient KV-centric LLM Serving System.
CoRR
Lian Liu, Shixin Zhao, Yutian Zhou, Yintao He, Mengdi Wang, Yinhe Han, Ying Wang
2026 J jnl
SAP: Shared-Aware Prefetching for Reducing Inter-Chiplet Data Access Latency.
IEEE Comput. Archit. Lett.
Junpei Huang, Haobo Xu, Yiming Gan, Ying Li, Wenhao Sun, Mengdi Wang, Xiaotong Wei, Feng Min, Ying Wang, Yinhe Han
2026 J jnl
SuperEncoder: Towards Efficient Neural Approximate Quantum State Preparation.
IEEE Trans. Computers
Yilun Zhao, Bingmeng Wang, Wenle Jiang, Xiwei Pan, Bing Li, Yinhe Han, Ying Wang
2026 J jnl
TriMoE: Augmenting GPU with AMX-Enabled CPU and DIMM-NDP for High-Throughput MoE Inference via Offloading.
CoRR
Yudong Pan, Yintao He, Tianhua Han, Lian Liu, Shixin Zhao, Zhirong Chen, Mengdi Wang, Cangyuan Li, Yinhe Han, Ying Wang
2025 J jnl
A Data-Centric Software-Hardware Co-Designed Architecture for Large-Scale Graph Processing.
IEEE Trans. Computers
Zerun Li, Xiaoming Chen, Yuxin Yang, Feng Min, Xiaoyu Zhang, Yinhe Han
2025 J jnl
A data-centric chip design agent framework for Verilog code generation.
ACM Trans. Design Autom. Electr. Syst.
Kaiyan Chang, Wenlong Zhu, Kun Wang, Xinyang He, Nan Yang, Zhirong Chen, Dantong Jin, Cangyuan Li, Yunhao Zhou, Hao Yan, Zhuoliang Zhao, Yuan Cheng, Mengdi Wang, Shengwen Liang, Yinhe Han, Xiaowei Li, Huawei Li, Ying Wang
2025 J jnl
ANNIE: Be Careful of Your Robots.
CoRR
Yiyang Huang, Zixuan Wang, Zishen Wan, Yapeng Tian, Haobo Xu, Yinhe Han, Yiming Gan
2025 — conf
Aphelios: A Selective Lock-step Neural Processing Unit Design.
ACM Great Lakes Symposium on VLSI
Wenhao Sun, Yiming Gan, Yuhui Hao, Yinhe Han
2025 J jnl
Attar: RRAM-based in-memory attention accelerator with software-hardware co-optimization.
Sci. China Inf. Sci.
Bing Li, Ying Qi, Ying Wang, Yinhe Han
2025 J jnl
AutoSilicon: Scaling Up RTL Design Generation Capability of Large Language Models.
ACM Trans. Design Autom. Electr. Syst.
Cangyuan Li, Chujie Chen, Yudong Pan, Wenjun Xu, Yiqi Liu, Kaiyan Chang, Yujie Wang, Mengdi Wang, Huawei Li, Yinhe Han, Ying Wang
2025 A* conf
BaWA: Automatic Optimizing Pruning Metric for Large Language Models with Balanced Weight and Activation.
ICML
Lian Liu, Xiandong Zhao, Guanchen Li, Dong Li, Mengdi Wang, Yinhe Han, Xiaowei Li, Ying Wang
2025 — conf
Be CIM or Be Memory: A Dual-mode-aware DNN Compiler for CIM Accelerators.
ASPLOS (2)
Shixin Zhao, Yuming Li, Bing Li, Yintao He, Mengdi Wang, Yinhe Han, Ying Wang
2025 J jnl
Be CIM or Be Memory: A Dual-mode-aware DNN Compiler for CIM Accelerators.
CoRR
Shixin Zhao, Yuming Li, Bing Li, Yintao He, Mengdi Wang, Yinhe Han, Ying Wang
2025 A* conf
CIM-BLAS: Computing-in-Memory Accelerator for BLAS.
DAC
Rui Liu, Zerun Li, Xiaoyu Zhang, Xiaoming Chen, Yinhe Han, Minghua Tang
2025 C conf
CIT-CTPlacer: An Analytical RDL Chiplet-Terminal Co-Placement Algorithm for Large-Scale 2.5D IC.
ISCAS
Xihao Liang, Yujie Wang, Xupengkai Lu, Lang Feng, Jixiang Zhu, Ying Wang, Yinhe Han
2025 A conf
CLASS: A Controller-Centric Layout Synthesizer for Dynamic Quantum Circuits.
ICCAD
Yu Chen, Yilun Zhao, Bing Li, He Li, Mengdi Wang, Yinhe Han, Ying Wang
2025 J jnl
CLASS: A Controller-Centric Layout Synthesizer for Dynamic Quantum Circuits.
CoRR
Yu Chen, Yilun Zhao, Bing Li, He Li, Mengdi Wang, Yinhe Han, Ying Wang
2025 — conf
COMET: Towards Practical W4A4KV4 LLMs Serving.
ASPLOS (2)
Lian Liu, Long Cheng, Haimeng Ren, Zhaohui Xu, Yudong Pan, Mengdi Wang, Xiaowei Li, Yinhe Han, Ying Wang
2025 J jnl
ChipSeek-R1: Generating Human-Surpassing RTL with LLM via Hierarchical Reward-Driven Reinforcement Learning.
CoRR
Zhirong Chen, Kaiyan Chang, Zhuolin Li, Xinyang He, Chujie Chen, Cangyuan Li, Mengdi Wang, Haobo Xu, Yinhe Han, Ying Wang
2025 — conf
Concurrency-Aware Cache Miss Cost Prediction with Perceptron Learning.
ACM Great Lakes Symposium on VLSI
Yuping Wu, Xiaoyang Lu, Xiaoming Chen, Yinhe Han, Xian-He Sun
2025 J jnl
DNA: A General Dynamic Neural Network Accelerator.
IEEE Trans. Computers
Lian Liu, Jinxin Yu, Mengdi Wang, Xiaowei Li, Yinhe Han, Ying Wang
2025 A* conf
Dadu-Corki: Algorithm-Architecture Co-Design for Embodied AI-powered Robotic Manipulation.
ISCA
Yiyang Huang, Yuhui Hao, Bo Yu, Feng Yan, Yuxin Yang, Feng Min, Yinhe Han, Lin Ma, Shaoshan Liu, Qiang Liu, Yiming Gan
2025 A* conf
Distributed-HISQ: A Distributed Quantum Control Architecture.
MICRO
Yilun Zhao, Kangding Zhao, Peng Zhou, Dingdong Liu, Tingyu Luo, Yuzhen Zheng, Peng Luo, Shun Hu, Jin Lin, Cheng Guo, Yinhe Han, Ying Wang, Mingtang Deng, Junjie Wu, Xiang Fu
2025 J jnl
Distributed-HISQ: A Distributed Quantum Control Architecture.
CoRR
Yilun Zhao, Kangding Zhao, Peng Zhou, Dingdong Liu, Tingyu Luo, Yuzhen Zheng, Peng Luo, Shun Hu, Jin Lin, Cheng Guo, Yinhe Han, Ying Wang, Mingtang Deng, Junjie Wu, Xiang Fu
2025 C conf
FlexIO: A Scalable IO Chiplet Architecture with Flexible Memory Controller Mapping.
ICCD
Junpei Huang, Haobo Xu, Ying Wang, Yinhe Han
2025 J jnl
HEAT: Efficient Vision Transformer Accelerator With Hybrid-Precision Quantization.
IEEE Trans. Circuits Syst. II Express Briefs
Pan Zhao, Donghui Xue, Licheng Wu, Liang Chang, Haining Tan, Yinhe Han, Jun Zhou
2025 J jnl
In-Memory Computing Accelerator for Iterative Linear Algebra Solvers.
IEEE Comput. Archit. Lett.
Rui Liu, Zerun Li, Xiaoyu Zhang, Xiaoming Chen, Yinhe Han, Minghua Tang
2025 A* conf
KARMA: Augmenting Embodied AI Agents with Long-and-Short Term Memory Systems.
ICRA
Zixuan Wang, Bo Yu, Junzhe Zhao, Wenhao Sun, Sai Hou, Shuai Liang, Xing Hu, Yinhe Han, Yiming Gan
2025 A* conf
LAD: Efficient Accelerator for Generative Inference of LLM with Locality Aware Decoding.
HPCA
Haoran Wang, Yuming Li, Haobo Xu, Ying Wang, Liqi Liu, Jun Yang, Yinhe Han
2025 J jnl
Large Processor Chip Model.
CoRR
Kaiyan Chang, Mingzhi Chen, Yunji Chen, Zhirong Chen, Dongrui Fan, Junfeng Gong, Nan Guo, Yinhe Han, Qinfen Hao, Shuo Hou, Xuanjing Huang, Pengwei Jin, Changxin Ke, Cangyuan Li, Guangli Li, Huawei Li, Kuan Li, Naipeng Li, Shengwen Liang, Cheng Liu, Hongwei Liu, Jiahua Liu, Junliang Lv, Jianan Mu, Jin Qin, Bin Sun, Chenxi Wang, Duo Wang, Mingjun Wang, Ying Wang, Chenggang Wu, Peiyang Wu, Teng Wu, Xiao Xiao, Mengyao Xie, Chenwei Xiong, Ruiyuan Xu, Mingyu Yan, Xiaochun Ye, Kuai Yu, Rui Zhang, Shuoming Zhang, Jiacheng Zhao
2025 J jnl
Low-Latency PIM Accelerator for Edge LLM Inference.
IEEE Comput. Archit. Lett.
Xinyu Wang, Xiaotian Sun, Wanqian Li, Feng Min, Xiaoyu Zhang, Xinjiang Zhang, Yinhe Han, Xiaoming Chen
2025 A* conf
Make LLM Inference Affordable to Everyone: Augmenting GPU Memory with NDP-DIMM.
HPCA
Lian Liu, Shixin Zhao, Bing Li, Haimeng Ren, Zhaohui Xu, Mengdi Wang, Xiaowei Li, Yinhe Han, Ying Wang
2025 J jnl
Make LLM Inference Affordable to Everyone: Augmenting GPU Memory with NDP-DIMM.
CoRR
Lian Liu, Shixin Zhao, Bing Li, Haimeng Ren, Zhaohui Xu, Mengdi Wang, Xiaowei Li, Yinhe Han, Ying Wang
2025 J jnl
PIMCOMP: An End-to-End DNN Compiler for Processing-In-Memory Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaotian Sun, Xinyu Wang, Wanqian Li, Yinhe Han, Xiaoming Chen
2025 J jnl
PIPECIM: Energy-Efficient Pipelined Computing-in-Memory Computation Engine With Sparsity-Aware Technique.
IEEE Trans. Very Large Scale Integr. Syst.
Yuanbo Wang, Liang Chang, Jingke Wang, Pan Zhao, Jiahao Zeng, Xin Zhao, Wuyang Hao, Liang Zhou, Haining Tan, Yinhe Han, Jun Zhou
2025 J jnl
ProMiner: Enhancing Locality, Parallelism, and Offloading for Graph Mining on Processing-in-Memory Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Liang Yan, Xiaoyang Lu, Sheng Xu, Xiaoming Chen, Xingqi Zou, Yinhe Han, Xian-He Sun
2025 J jnl
Pyramid: Accelerating LLM Inference With Cross-Level Processing-in-Memory.
IEEE Comput. Archit. Lett.
Liang Yan, Xiaoyang Lu, Xiaoming Chen, Yinhe Han, Xian-He Sun
2025 — conf
RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework.
ASP-DAC
Kun Wang, Kaiyan Chang, Mengdi Wang, Xingqi Zou, Haobo Xu, Yinhe Han, Ying Wang
2025 J jnl
RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework.
CoRR
Kun Wang, Kaiyan Chang, Mengdi Wang, Xinqi Zou, Haobo Xu, Yinhe Han, Ying Wang
2025 A conf
RTPU: Unifying Non-Private and Private Inference with Reconfigurable Architecture.
ICCAD
Fuping Li, Ying Wang, Yinghao Yang, Jingxuan Li, Yibo Du, Huawei Li, Yinhe Han, Hang Lu, Xiaowei Li
2025 J jnl
Re-Meltrix: A Reconfigurable Processing-in-Memory Architecture Based on RRAM and Function Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Boyu Long, Yinhe Han, Xian-He Sun, Xiaoming Chen
2025 J jnl
Resister: A Resilient Interposer Architecture for Chiplet to Mitigate Timing Side-Channel Attacks.
ACM Trans. Design Autom. Electr. Syst.
Xinrui Wang, Lang Feng, Yujie Wang, Taotao Xu, Yinhe Han, Zhongfeng Wang
2024 — conf
ACES: Accelerating Sparse Matrix Multiplication with Adaptive Execution Flow and Concurrency-Aware Cache Optimizations.
ASPLOS (3)
Xiaoyang Lu, Boyu Long, Xiaoming Chen, Yinhe Han, Xian-He Sun
2024 C conf
Accelerating Frequency-domain Convolutional Neural Networks Inference using FPGAs.
ISCAS
Yi Chen, Bosheng Liu, Yongqi Xu, Jigang Wu, Xiaoming Chen, Peng Liu, Qingguo Zhou, Yinhe Han
2024 C conf
AceMiner: Accelerating Graph Pattern Matching using PIM with Optimized Cache System.
ICCD
Liang Yan, Xiaoyang Lu, Xiaoming Chen, Sheng Xu, Xingqi Zou, Yinhe Han, Xian-He Sun
2024 J jnl
An Automatic Neural Network Architecture-and-Quantization Joint Optimization Framework for Efficient Model Inference.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lian Liu, Ying Wang, Xiandong Zhao, Weiwei Chen, Huawei Li, Xiaowei Li, Yinhe Han
2024 A conf
Benchmarking and Optimizing Federated Learning with Hardware-related Metrics.
BMVC
Kai Pan, Yapeng Tian, Yinhe Han, Yiming Gan
2024 J jnl
BitQ: Tailoring Block Floating Point Precision for Improved DNN Efficiency on Resource-Constrained Devices.
CoRR
Yongqi Xu, Yujian Lee, Gao Yi, Bosheng Liu, Yucong Chen, Peng Liu, Jigang Wu, Xiaoming Chen, Yinhe Han
2024 J jnl
COMET: Towards Partical W4A4KV4 LLMs Serving.
CoRR
Lian Liu, Haimeng Ren, Long Cheng, Zhaohui Xu, Yudong Pan, Mengdi Wang, Xiaowei Li, Yinhe Han, Ying Wang
2024 B conf
Chipletizer: Repartitioning SoCs for Cost-Effective Chiplet Integration.
ASPDAC
Fuping Li, Ying Wang, Yujie Wang, Mengdi Wang, Yinhe Han, Huawei Li, Xiaowei Li
2024 A* conf
Chiplever: Towards Effortless Extension of Chiplet-based System for FHE.
DAC
Yibo Du, Ying Wang, Bing Li, Fuping Li, Shengwen Liang, Huawei Li, Xiaowei Li, Yinhe Han
2024 J jnl
Corki: Enabling Real-time Embodied AI Robots via Algorithm-Architecture Co-Design.
CoRR
Yiyang Huang, Yuhui Hao, Bo Yu, Feng Yan, Yuxin Yang, Feng Min, Yinhe Han, Lin Ma, Shaoshan Liu, Qiang Liu, Yiming Gan
2024 J jnl
Crypto-DSEDA: A Domain-Specific EDA Flow for CiM-Based Cryptographic Accelerators.
IEEE Des. Test
Rui Liu, Zerun Li, Xiaoyu Zhang, Wanqian Li, Libo Shen, Rui Tang, Zhejian Luo, Xiaoming Chen, Yinhe Han, Minghua Tang
2024 J jnl
DaDu-E: Rethinking the Role of Large Language Model in Robotic Computing Pipeline.
CoRR
Wenhao Sun, Sai Hou, Zixuan Wang, Bo Yu, Shaoshan Liu, Xu Yang, Shuai Liang, Yiming Gan, Yinhe Han
2024 A* conf
Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework.
DAC
Kaiyan Chang, Kun Wang, Nan Yang, Ying Wang, Dantong Jin, Wenlong Zhu, Zhirong Chen, Cangyuan Li, Hao Yan, Yunhao Zhou, Zhuoliang Zhao, Yuan Cheng, Yudong Pan, Yiqi Liu, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, Xiaowei Li
2024 J jnl
Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework.
CoRR
Kaiyan Chang, Kun Wang, Nan Yang, Ying Wang, Dantong Jin, Wenlong Zhu, Zhirong Chen, Cangyuan Li, Hao Yan, Yunhao Zhou, Zhuoliang Zhao, Yuan Cheng, Yudong Pan, Yiqi Liu, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, Xiaowei Li
2024 — conf
Depth-NeuS: Neural Implicit Surfaces Learning for Multi-view Reconstruction Based on Depth Information Optimization.
ICIC (5)
Siqi Wen, Hanqi Jiang, Cheng Zeng, Runnan Chen, Jidong Yuan, Shuai Liang, Yinhe Han
2024 A* conf
Drift: Leveraging Distribution-based Dynamic Precision Quantization for Efficient Deep Neural Network Acceleration.
DAC
Lian Liu, Zhaohui Xu, Yintao He, Ying Wang, Huawei Li, Xiaowei Li, Yinhe Han
2024 J jnl
FPIA: Communication-Aware Multi-Chiplet Integration With Field-Programmable Interconnect Fabric on Reusable Silicon Interposer.
IEEE Trans. Circuits Syst. I Regul. Pap.
Bo Jiao, Lei Xu, Xinyu Yu, Haitao Yang, Haozhe Zhu, Yu Wang, Jundong Zhu, Dexin Wen, Lingli Wang, Jun Tao, Chixiao Chen, Yinhe Han, Qi Liu, Ninghui Sun, Ming Liu
2024 J jnl
GAS: General-Purpose In-Memory-Computing Accelerator for Sparse Matrix Multiplication.
IEEE Trans. Computers
Xiaoyu Zhang, Zerun Li, Rui Liu, Xiaoming Chen, Yinhe Han
2024 A conf
GPACE: An Energy-Efficient PQ-Based GCN Accelerator with Redundancy Reduction.
DATE
Yibo Du, Shengwen Liang, Ying Wang, Huawei Li, Xiaowei Li, Yinhe Han
2024 — conf
HEX-SIM: Evaluating Multi-modal Large Language Models on Multi-chiplet NPUs.
IISWC
Xinquan Lin, Haobo Xu, Yinhe Han, Yiming Gan
2024 J jnl
JANM-IK: Jacobian Argumented Nelder-Mead Algorithm for Inverse Kinematics and its Hardware Acceleration.
IEEE Comput. Archit. Lett.
Yuxin Yang, Xiaoming Chen, Yinhe Han
2024 J jnl
KARMA: Augmenting Embodied AI Agents with Long-and-short Term Memory Systems.
CoRR
Zixuan Wang, Bo Yu, Junzhe Zhao, Wenhao Sun, Sai Hou, Shuai Liang, Xing Hu, Yinhe Han, Yiming Gan
2024 J jnl
Mathematical Framework for Optimizing Crossbar Allocation for ReRAM-based CNN Accelerators.
ACM Trans. Design Autom. Electr. Syst.
Wanqian Li, Yinhe Han, Xiaoming Chen
2024 C conf
MemSort: In-Memory Sorting Architecture.
ICCD
Rui Liu, Xiaoyu Zhang, Xinyu Wang, Feng Min, Zhejian Luo, Xiaoming Chen, Yinhe Han, Minghua Tang
2024 A conf
Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation.
ICCAD
Kaiyan Chang, Zhirong Chen, Yunhao Zhou, Wenlong Zhu, Kun Wang, Haobo Xu, Cangyuan Li, Mengdi Wang, Shengwen Liang, Huawei Li, Yinhe Han, Ying Wang
2024 J jnl
Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation.
CoRR
Kaiyan Chang, Zhirong Chen, Yunhao Zhou, Wenlong Zhu, Kun Wang, Haobo Xu, Cangyuan Li, Mengdi Wang, Shengwen Liang, Huawei Li, Yinhe Han, Ying Wang
2024 — conf
ORIANNA: An Accelerator Generation Framework for Optimization-based Robotic Applications.
ASPLOS (2)
Yuhui Hao, Yiming Gan, Bo Yu, Qiang Liu, Yinhe Han, Zishen Wan, Shaoshan Liu
2024 J jnl
PIMCOMP: An End-to-End DNN Compiler for Processing-In-Memory Accelerators.
CoRR
Xiaotian Sun, Xinyu Wang, Wanqian Li, Yinhe Han, Xiaoming Chen
2024 A conf
PIMSIM-NN: An ISA-based Simulation Framework for Processing-in-Memory Accelerators.
DATE
Xinyu Wang, Xiaotian Sun, Yinhe Han, Xiaoming Chen
2024 J jnl
PIMSIM-NN: An ISA-based Simulation Framework for Processing-in-Memory Accelerators.
CoRR
Xinyu Wang, Xiaotian Sun, Yinhe Han, Xiaoming Chen
2024 A conf
PIMSYN: Synthesizing Processing-in-Memory CNN Accelerators.
DATE
Wanqian Li, Xiaotian Sun, Xinyu Wang, Lei Wang, Yinhe Han, Xiaoming Chen
2024 J jnl
PIMSYN: Synthesizing Processing-in-memory CNN Accelerators.
CoRR
Wanqian Li, Xiaotian Sun, Xinyu Wang, Lei Wang, Yinhe Han, Xiaoming Chen
2024 — conf
PrimePar: Efficient Spatial-temporal Tensor Partitioning for Large Transformer Model Training.
ASPLOS (3)
Haoran Wang, Lei Wang, Haobo Xu, Ying Wang, Yuming Li, Yinhe Han
2024 J jnl
SuperEncoder: Towards Universal Neural Approximate Quantum State Preparation.
CoRR
Yilun Zhao, Bingmeng Wang, Wenle Jiang, Xiwei Pan, Bing Li, Yinhe Han, Ying Wang
2024 A* conf
TMiner: A Vertex-Based Task Scheduling Architecture for Graph Pattern Mining.
MICRO
Zerun Li, Xiaoming Chen, Yinhe Han
2023 A* conf
APPEND: Rethinking ASIP Synthesis in the Era of AI.
DAC
Cangyuan Li, Ying Wang, Huawei Li, Yinhe Han
2023 — conf
Accelerating Convolutional Neural Networks in Frequency Domain via Kernel-Sharing Approach.
ASP-DAC
Bosheng Liu, Hongyi Liang, Jigang Wu, Xiaoming Chen, Peng Liu, Yinhe Han
2023 A* conf
CTA: Hardware-Software Co-design for Compressed Token Attention Mechanism.
HPCA
Haoran Wang, Haobo Xu, Ying Wang, Yinhe Han
2023 J jnl
ChipGPT: How far are we from natural language hardware design.
CoRR
Kaiyan Chang, Ying Wang, Haimeng Ren, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, Xiaowei Li
2023 A* conf
Dadu-RBD: Robot Rigid Body Dynamics Accelerator with Multifunctional Pipelines.
MICRO
Yuxin Yang, Xiaoming Chen, Yinhe Han
2023 J jnl
Depth-NeuS: Neural Implicit Surfaces Learning for Multi-view Reconstruction Based on Depth Information Optimization.
CoRR
Hanqi Jiang, Cheng Zeng, Runnan Chen, Shuai Liang, Yinhe Han, Yichao Gao, Conglin Wang
2023 A conf
ENASA: Towards Edge Neural Architecture Search based on CIM acceleration.
DATE
Shixin Zhao, Songyun Qu, Ying Wang, Yinhe Han
2023 A* conf
FSPA: An FeFET-based Sparse Matrix-Dense Vector Multiplication Accelerator.
DAC
Xiaoyu Zhang, Zerun Li, Rui Liu, Xiaoming Chen, Yinhe Han
2023 J jnl
FeCrypto: Instruction Set Architecture for Cryptographic Algorithms Based on FeFET-Based In-Memory Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rui Liu, Xiaoyu Zhang, Zhiwen Xie, Xinyu Wang, Zerun Li, Xiaoming Chen, Yinhe Han, Minghua Tang
2023 J jnl
Frequency-Domain Inference Acceleration for Convolutional Neural Networks Using ReRAMs.
IEEE Trans. Parallel Distributed Syst.
Bosheng Liu, Zhuoshen Jiang, Yalan Wu, Jigang Wu, Xiaoming Chen, Peng Liu, Qingguo Zhou, Yinhe Han
2023 A conf
Full State Quantum Circuit Simulation Beyond Memory Limit.
ICCAD
Yilun Zhao, Yu Chen, He Li, Ying Wang, Kaiyan Chang, Bingmeng Wang, Bing Li, Yinhe Han
2023 C conf
Hardware-Software Co-Design for Content-Based Sparse Attention.
ICCD
Rui Tang, Xiaoyu Zhang, Rui Liu, Zhejian Luo, Xiaoming Chen, Yinhe Han
2023 J jnl
IVP: An Intelligent Video Processing Architecture for Video Streaming.
IEEE Trans. Computers
Chengsi Gao, Ying Wang, Yinhe Han, Weiwei Chen, Lei Zhang
2023 A conf
LIM-GEN: A Data-Guided Framework for Automated Generation of Heterogeneous Logic-in-Memory Architecture.
ICCAD
Libo Shen, Boyu Long, Rui Liu, Xiaoyu Zhang, Yinhe Han, Xiaoming Chen
2023 A conf
Layer-Puzzle: Allocating and Scheduling Multi-task on Multi-core NPUs by Using Layer Heterogeneity.
DATE
Chengsi Gao, Ying Wang, Cheng Liu, Mengdi Wang, Weiwei Chen, Yinhe Han, Lei Zhang
2023 A conf
Meltrix: A RRAM-Based Polymorphic Architecture Enhanced by Function Synthesis.
ICCAD
Boyu Long, Libo Shen, Xiaoyu Zhang, Yinhe Han, Xian-He Sun, Xiaoming Chen
2023 C conf
PANG: A Pattern-Aware GCN Accelerator for Universal Graphs.
ICCD
Yibo Du, Ying Wang, Shengwen Liang, Huawei Li, Xiaowei Li, Yinhe Han
2023 A* conf
PIMCOMP: A Universal Compilation Framework for Crossbar-based PIM DNN Accelerators.
DAC
Xiaotian Sun, Xinyu Wang, Wanqian Li, Lei Wang, Yinhe Han, Xiaoming Chen
2023 J jnl
PIMCOMP: A Universal Compilation Framework for Crossbar-based PIM DNN Accelerators.
CoRR
Xiaotian Sun, Xinyu Wang, Wanqian Li, Lei Wang, Yinhe Han, Xiaoming Chen
2023 J jnl
RBDCore: Robot Rigid Body Dynamics Accelerator with Multifunctional Pipelines.
CoRR
Yuxin Yang, Xiaoming Chen, Yinhe Han
2022 A* conf
AGNAS: Attention-Guided Micro and Macro-Architecture Search.
ICML
Zihao Sun, Yu Hu, Shun Lu, Longxing Yang, Jilin Mei, Yinhe Han, Xiaowei Li
2022 — conf
AIC-Bench: Workload Selection Methodology for Benchmarking AI Chips.
HPCC/DSS/SmartCity/DependSys
Zhenyu Quan, Xiaoming Chen, Yinhe Han
2022 J jnl
Amphis: Managing Reconfigurable Processor Architectures With Generative Adversarial Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Weiwei Chen, Ying Wang, Ying Xu, Chengsi Gao, Yinhe Han, Lei Zhang
2022 B conf
Closing the Dynamics Gap via Adversarial and Reinforcement Learning for High-Speed Racing.
IJCNN
Jingyu Niu, Yu Hu, Wei Li, Guangyan Huang, Yinhe Han, Xiaowei Li
2022 J jnl
Dadu-SV: Accelerate Stereo Vision Processing on NPU.
IEEE Embed. Syst. Lett.
Feng Min, Ying Wang, Haobo Xu, Junpei Huang, Yujie Wang, Xingqi Zou, Meixuan Lu, Yinhe Han
2022 A* conf
DeepBurning-SEG: Generating DNN Accelerators of Segment-Grained Pipeline Architecture.
MICRO
Xuyi Cai, Ying Wang, Xiaohan Ma, Yinhe Han, Lei Zhang
2022 — conf
Energy-Efficient In-SRAM Accumulation for CMOS-based CNN Accelerators.
ACM Great Lakes Symposium on VLSI
Wanqian Li, Yinhe Han, Xiaoming Chen
2022 J jnl
Fast and High-Accuracy Approximate MAC Unit Design for CNN Computing.
IEEE Embed. Syst. Lett.
Hang Xiao, Haobo Xu, Xiaoming Chen, Yujie Wang, Yinhe Han
2022 — conf
FeMIC: Multi-Operands in-Memory Computing Based on FeFETs.
ASP-DAC
Rui Liu, Xiaoyu Zhang, Xiaoming Chen, Yinhe Han, Minghua Tang
2022 A conf
GIA: A Reusable General Interposer Architecture for Agile Chiplet Integration.
ICCAD
Fuping Li, Ying Wang, Yuanqing Cheng, Yujie Wang, Yinhe Han, Huawei Li, Xiaowei Li
2022 A* conf
GraphRing: an HMC-ring based graph processing framework with optimized data movement.
DAC
Zerun Li, Xiaoming Chen, Yinhe Han
2022 J jnl
LINAC: A Spatially Linear Accelerator for Convolutional Neural Networks.
IEEE Comput. Archit. Lett.
Hang Xiao, Haobo Xu, Ying Wang, Yujie Wang, Yinhe Han
2022 J jnl
Load Balance Guaranteed Vehicle-to-Vehicle Computation Offloading for Min-Max Fairness in VANETs.
IEEE Trans. Intell. Transp. Syst.
Yalan Wu, Jigang Wu, Long Chen, Jiaquan Yan, Yinhe Han
2022 J jnl
Neural-PIM: Efficient Processing-In-Memory With Neural Approximation of Peripherals.
IEEE Trans. Computers
Weidong Cao, Yilong Zhao, Adith Boloor, Yinhe Han, Xuan Zhang, Li Jiang
2022 J jnl
Neural-PIM: Efficient Processing-In-Memory with Neural Approximation of Peripherals.
CoRR
Weidong Cao, Yilong Zhao, Adith Boloor, Yinhe Han, Xuan Zhang, Li Jiang
2022 — conf
Optimal Data Allocation for Graph Processing in Processing-in-Memory Systems.
ASP-DAC
Zerun Li, Xiaoming Chen, Yinhe Han
2022 — conf
P3S: A High Accuracy Probabilistic Prediction Processing System for CNN Acceleration.
ACM Great Lakes Symposium on VLSI
Hang Xiao, Haobo Xu, Xiaoming Chen, Yujie Wang, Yinhe Han
2022 — conf
PME: Processing-in-memory Masking and Encoding for Secure NVM.
HPCC/DSS/SmartCity/DependSys
Zhiwen Xie, Yinhe Han, Xiaoming Chen
2022 J jnl
Re-FeMAT: A Reconfigurable Multifunctional FeFET-Based Memory Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaoyu Zhang, Rui Liu, Tao Song, Yuxin Yang, Yinhe Han, Xiaoming Chen
2022 J jnl
Reconfiguration algorithms for synchronous communication on switch based degradable arrays.
Parallel Comput.
Yalan Wu, Jigang Wu, Peng Liu, Yinhe Han, Thambipillai Srikanthan
2022 J jnl
STC-NAS: Fast neural architecture search with source-target consistency.
Neurocomputing
Zihao Sun, Yu Hu, Longxing Yang, Shun Lu, Jilin Mei, Yinhe Han, Xiaowei Li
2022 J jnl
Search-Free Inference Acceleration for Sparse Convolutional Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bosheng Liu, Xiaoming Chen, Yinhe Han, Jigang Wu, Liang Chang, Peng Liu, Haobo Xu
2022 A* conf
Searching for BurgerFormer with Micro-Meso-Macro Space Design.
ICML
Longxing Yang, Yu Hu, Shun Lu, Zihao Sun, Jilin Mei, Yinhe Han, Xiaowei Li
2022 — conf
Solving Least-Squares Fitting in $O(1)$ Using RRAM-based Computing-in-Memory Technique.
ASP-DAC
Xiaoming Chen, Yinhe Han
2022 J jnl
Survey on chiplets: interface, interconnect and integration methodology.
CCF Trans. High Perform. Comput.
Xiaohan Ma, Ying Wang, Yujie Wang, Xuyi Cai, Yinhe Han
2022 J jnl
Toward Efficient Computing for Robotics: From a Circuit and System View.
IEEE Trans. Circuits Syst. II Express Briefs
Haobo Xu, Yuxin Yang, Feng Min, Junpei Huang, Xiaoming Chen, Yinhe Han, Ninghui Sun
2021 A* conf
BRAHMS: Beyond Conventional RRAM-based Neural Network Accelerators Using Hybrid Analog Memory System.
DAC
Tao Song, Xiaoming Chen, Xiaoyu Zhang, Yinhe Han
2021 J jnl
Breaking the von Neumann bottleneck: architecture-level processing-in-memory technology.
Sci. China Inf. Sci.
Xingqi Zou, Sheng Xu, Xiaoming Chen, Liang Yan, Yinhe Han
2021 A conf
CoPIM: A Concurrency-aware PIM Workload Offloading Architecture for Graph Applications.
ISLPED
Liang Yan, Mingzhe Zhang, Rujia Wang, Xiaoming Chen, Xingqi Zou, Xiaoyang Lu, Yinhe Han, Xian-He Sun
2021 C conf
DDSAS: Dynamic and Differentiable Space-Architecture Search.
ACML
Longxing Yang, Yu Hu, Shun Lu, Zihao Sun, Jilin Mei, Yiming Zeng, Zhiping Shi, Yinhe Han, Xiaowei Li
2021 J jnl
Dadu-Eye: A 5.3 TOPS/W, 30 fps/1080p High Accuracy Stereo Vision Accelerator.
IEEE Trans. Circuits Syst. I Regul. Pap.
Feng Min, Haobo Xu, Ying Wang, Yujie Wang, Jiajun Li, Xingqi Zou, Bei Li, Yinhe Han
2021 J jnl
Defect Analysis and Parallel Testing for 3D Hybrid CMOS-Memristor Memory.
IEEE Trans. Emerg. Top. Comput.
Peng Liu, Zhiqiang You, Jigang Wu, Michael Elimu, Weizheng Wang, Shuo Cai, Yinhe Han
2021 J jnl
Design and Analysis of Energy-Efficient Dynamic Range Approximate Logarithmic Multipliers for Machine Learning.
IEEE Trans. Sustain. Comput.
Peipei Yin, Chenghua Wang, Haroon Waris, Weiqiang Liu, Yinhe Han, Fabrizio Lombardi
2021 — conf
Eliminating Iterations of Iterative Methods: Solving Large-Scale Sparse Linear System in
ACM Great Lakes Symposium on VLSI
Tao Song, Xiaoming Chen, Yinhe Han
2021 A* conf
F3D: Accelerating 3D Convolutional Neural Networks in Frequency Space Using ReRAM.
DAC
Bosheng Liu, Zhuoshen Jiang, Jigang Wu, Xiaoming Chen, Yinhe Han, Peng Liu
2021 J jnl
Fault Modeling and Efficient Testing of Memristor-Based Memory.
IEEE Trans. Circuits Syst. I Regul. Pap.
Peng Liu, Zhiqiang You, Jigang Wu, Bosheng Liu, Yinhe Han, Krishnendu Chakrabarty
2021 — conf
FePIM: Contention-Free In-Memory Computing Based on Ferroelectric Field-Effect Transistors.
ASP-DAC
Xiaoming Chen, Yuping Wu, Yinhe Han
2021 J jnl
Integrating Two Logics Into One Crossbar Array for Logic Gate Design.
IEEE Trans. Circuits Syst. II Express Briefs
Lian Yao, Peng Liu, Jigang Wu, Yinhe Han, Yuehang Zhong, Zhiqiang You
2021 A* conf
KFS-LIO: Key-Feature Selection for Lightweight Lidar Inertial Odometry.
ICRA
Wei Li, Yu Hu, Yinhe Han, Xiaowei Li
2021 — conf
RRAM-based Analog In-Memory Computing : Invited Paper.
NANOARCH
Xiaoming Chen, Tao Song, Yinhe Han
2020 — conf
Accelerating RRT Motion Planning Using TCAM.
ACM Great Lakes Symposium on VLSI
Yuxin Yang, Shiqi Lian, Xiaoming Chen, Yinhe Han
2020 A* conf
An Efficient Deep Learning Accelerator for Compressed Video Analysis.
DAC
Yongchen Wang, Ying Wang, Huawei Li, Yinhe Han, Xiaowei Li
2020 J jnl
Architecting Effectual Computation for Machine Learning Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hang Lu, Mingzhe Zhang, Yinhe Han, Qi Wang, Huawei Li, Xiaowei Li
2020 A* conf
Communication Lower Bound in Convolution Accelerators.
HPCA
Xiaoming Chen, Yinhe Han, Yu Wang
2020 A conf
DaDu Series - Fast and Efficient Robot Accelerators.
ICCAD
Yinhe Han, Yuxin Yang, Xiaoming Chen, Shiqi Lian
2020 A* conf
Dadu-CD: Fast and Efficient Processing-in-Memory Accelerator for Collision Detection.
DAC
Yuxin Yang, Xiaoming Chen, Yinhe Han
2020 A* conf
Exploring Spatial-Temporal Multi-Frequency Analysis for High-Fidelity and Temporal-Consistency Video Prediction.
CVPR
Beibei Jin, Yu Hu, Qiankun Tang, Jingyu Niu, Zhiping Shi, Yinhe Han, Xiaowei Li
2020 J jnl
Exploring Spatial-Temporal Multi-Frequency Analysis for High-Fidelity and Temporal-Consistency Video Prediction.
CoRR
Beibei Jin, Yu Hu, Qiankun Tang, Jingyu Niu, Zhiping Shi, Yinhe Han, Xiaowei Li
2020 — conf
GNN-PIM: A Processing-in-Memory Architecture for Graph Neural Networks.
ACA
Zhao Wang, Yijin Guan, Guangyu Sun, Dimin Niu, Yuhao Wang, Hongzhong Zheng, Yinhe Han
2020 A* conf
PIM-Prune: Fine-Grain DCNN Pruning for Crossbar-Based Process-In-Memory Architecture.
DAC
Chaoqun Chu, Yanzhi Wang, Yilong Zhao, Xiaolong Ma, Shaokai Ye, Yunyan Hong, Xiaoyao Liang, Yinhe Han, Li Jiang
2020 — conf
Search-free Accelerator for Sparse Convolutional Neural Networks.
ASP-DAC
Bosheng Liu, Xiaoming Chen, Yinhe Han, Ying Wang, Jiajun Li, Haobo Xu, Xiaowei Li
2020 J jnl
Swallow: A Versatile Accelerator for Sparse Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bosheng Liu, Xiaoming Chen, Yinhe Han, Haobo Xu
2020 — conf
TUPIM: A Transparent and Universal Processing-in-Memory Architecture for Unmodified Binaries.
ACM Great Lakes Symposium on VLSI
Sheng Xu, Xiaoming Chen, Xuehai Qian, Yinhe Han
2020 B conf
Two-Stage Safe Reinforcement Learning for High-Speed Autonomous Racing.
SMC
Jingyu Niu, Yu Hu, Beibei Jin, Yinhe Han, Xiaowei Li
2019 A conf
ACG-Engine: An Inference Accelerator for Content Generative Neural Networks.
ICCAD
Haobo Xu, Ying Wang, Yujie Wang, Jiajun Li, Bosheng Liu, Yinhe Han
2019 J jnl
Accelerating DNN-based 3D point cloud processing for mobile computing.
Sci. China Inf. Sci.
Bosheng Liu, Xiaoming Chen, Yinhe Han, Jiajun Li, Haobo Xu, Xiaowei Li
2019 — conf
Addressing the issue of processing element under-utilization in general-purpose systolic deep learning accelerators.
ASP-DAC
Bosheng Liu, Xiaoming Chen, Ying Wang, Yinhe Han, Jiajun Li, Haobo Xu, Xiaowei Li
2019 A conf
China Test Conference (CTC) - Extending the Global Test Forum to China.
ITC
Huawei Li, Xiaowei Li, Yinhe Han
2019 J jnl
Communication Lower Bound in Convolution Accelerators.
CoRR
Xiaoming Chen, Yinhe Han, Yu Wang
2019 — conf
CuckooPIM: an efficient and less-blocking coherence mechanism for processing-in-memory systems.
ASP-DAC
Sheng Xu, Xiaoming Chen, Ying Wang, Yinhe Han, Xiaowei Li
2019 C conf
FeMAT: Exploring In-Memory Processing in Multifunctional FeFET-Based Memory Array.
ICCD
Xiaoyu Zhang, Xiaoming Chen, Yinhe Han
2019 — conf
Implementation of Parametric Hardware Trojan in FPGA.
ITC-Asia
Yipei Yang, Jing Ye, Xiaowei Li, Yinhe Han, Huawei Li, Yu Hu
2019 A* conf
Merging Everything (ME): A Unified FPGA Architecture Based on Logic-in-Memory Techniques.
DAC
Xiaoming Chen, Longxiang Yin, Bosheng Liu, Yinhe Han
2019 J jnl
PIMSim: A Flexible and Detailed Processing-in-Memory Simulator.
IEEE Comput. Archit. Lett.
Sheng Xu, Xiaoming Chen, Ying Wang, Yinhe Han, Xuehai Qian, Xiaowei Li
2019 J jnl
Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xiaoming Chen, Kai Ni, Michael T. Niemier, Yinhe Han, Suman Datta, Xiaobo Sharon Hu
2019 — conf
Simulate-the-hardware: training accurate binarized neural networks for low-precision neural accelerators.
ASP-DAC
Jiajun Li, Ying Wang, Bosheng Liu, Yinhe Han, Xiaowei Li
2019 A* conf
System-level hardware failure prediction using deep learning.
DAC
Xiaoyi Sun, Krishnendu Chakrabarty, Ruirui Huang, Yiquan Chen, Bing Zhao, Hai Cao, Yinhe Han, Xiaoyao Liang, Li Jiang
2019 J jnl
Thread: Towards fine-grained precision reconfiguration in variable-precision neural network accelerator.
IEICE Electron. Express
Shichang Zhang, Ying Wang, Xiaoming Chen, Yinhe Han, Yujie Wang, Xiaowei Li
2019 J jnl
moDNN: Memory Optimal Deep Neural Network Training on Graphics Processing Units.
IEEE Trans. Parallel Distributed Syst.
Xiaoming Chen, Danny Ziyi Chen, Yinhe Han, Xiaobo Sharon Hu
2018 J jnl
A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ying Wang, Huawei Li, Yinhe Han, Xiaowei Li
2018 A conf
A retrospective evaluation of energy-efficient object detection solutions on embedded devices.
DATE
Ying Wang, Zhenyu Quan, Jiajun Li, Yinhe Han, Huawei Li, Xiaowei Li
2018 J jnl
CPicker: Leveraging Performance-Equivalent Configurations to Improve Data Center Energy Efficiency.
J. Comput. Sci. Technol.
Faqiang Sun, Guihai Yan, Xin He, Huawei Li, Yinhe Han
2018 A* conf
Dadu-P: a scalable accelerator for robot motion planning in a dynamic environment.
DAC
Shiqi Lian, Yinhe Han, Xiaoming Chen, Ying Wang, Hang Xiao
2018 J jnl
DimRouter: A Multi-Mode Router Architecture for Higher Energy-Proportionality of On-Chip Networks.
J. Comput. Sci. Technol.
Shiqi Lian, Ying Wang, Yinhe Han
2018 — conf
PIMCH: Cooperative memory prefetching in processing-in-memory architecture.
ASP-DAC
Sheng Xu, Ying Wang, Yinhe Han, Xiaowei Li
2018 J jnl
RT3D: Real-Time 3-D Vehicle Detection in LiDAR Point Cloud for Autonomous Driving.
IEEE Robotics Autom. Lett.
Yiming Zeng, Yu Hu, Shice Liu, Jing Ye, Yinhe Han, Xiaowei Li, Ninghui Sun
2018 A* conf
See and Think: Disentangling Semantic Scene Completion.
NeurIPS
Shice Liu, Yu Hu, Yiming Zeng, Qiankun Tang, Beibei Jin, Yinhe Han, Xiaowei Li
2017 — conf
ApproxEye: Enabling approximate computation reuse for microrobotic computer vision.
ASP-DAC
Xin He, Guihai Yan, Faqiang Sun, Yinhe Han, Xiaowei Li
2017 — conf
BoDNoC: Providing bandwidth-on-demand interconnection for multi-granularity memory systems.
ASP-DAC
Shiqi Lian, Ying Wang, Yinhe Han, Xiaowei Li
2017 — conf
CNN-based object detection solutions for embedded heterogeneous multicore SoCs.
ASP-DAC
Cheng Wang, Ying Wang, Yinhe Han, Lili Song, Zhenyu Quan, Jiajun Li, Xiaowei Li
2017 A* conf
Dadu: Accelerating Inverse Kinematics for High-DOF Robots.
DAC
Shiqi Lian, Yinhe Han, Ying Wang, Yungang Bao, Hang Xiao, Xiaowei Li, Ninghui Sun
2017 J jnl
Exploiting the Potential of Computation Reuse Through Approximate Computing.
IEEE Trans. Multi Scale Comput. Syst.
Xin He, Shuhao Jiang, Wenyan Lu, Guihai Yan, Yinhe Han, Xiaowei Li
2017 A* conf
FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks.
HPCA
Wenyan Lu, Guihai Yan, Jiajun Li, Shijun Gong, Yinhe Han, Xiaowei Li
2017 J jnl
PowerTrader: Enforcing Autonomous Power Management for Future Large-Scale Many-Core Processors.
IEEE Trans. Multi Scale Comput. Syst.
Hang Lu, Guihai Yan, Yinhe Han, Xiaowei Li
2017 J jnl
Retention-Aware DRAM Assembly and Repair for Future FGR Memories.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ying Wang, Yinhe Han, Cheng Wang, Huawei Li, Xiaowei Li
2017 J jnl
STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator.
IEEE Trans. Very Large Scale Integr. Syst.
Lili Song, Ying Wang, Yinhe Han, Huawei Li, Yuanqing Cheng, Xiaowei Li
2016 J jnl
A Cost-Effective Energy Optimization Framework of Multicore SoCs Based on Dynamically Reconfigurable Voltage-Frequency Islands.
ACM Trans. Design Autom. Electr. Syst.
Song Jin, Songwei Pei, Yinhe Han, Huawei Li
2016 — conf
ACR: Enabling computation reuse for approximate computing.
ASP-DAC
Xin He, Guihai Yan, Yinhe Han, Xiaowei Li
2016 J jnl
An Analytical Framework for Estimating Scale-Out and Scale-Up Power Efficiency of Heterogeneous Manycores.
IEEE Trans. Computers
Jun Ma, Guihai Yan, Yinhe Han, Xiaowei Li
2016 A* conf
C-brain: a deep learning accelerator that tames the diversity of CNNs through adaptive data-level parallelization.
DAC
Lili Song, Ying Wang, Yinhe Han, Xin Zhao, Bosheng Liu, Xiaowei Li
2016 A* conf
DISCO: a low overhead in-network data compressor for energy-efficient chip multi-processors.
DAC
Ying Wang, Yinhe Han, Jun Zhou, Huawei Li, Xiaowei Li
2016 A* conf
DeepBurning: automatic generation of FPGA-based learning accelerators for the neural network family.
DAC
Ying Wang, Jie Xu, Yinhe Han, Huawei Li, Xiaowei Li
2016 J jnl
EcoUp: Towards Economical Datacenter Upgrading.
IEEE Trans. Parallel Distributed Syst.
Guihai Yan, Jun Ma, Yinhe Han, Xiaowei Li
2016 J jnl
Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation.
IEEE Trans. Very Large Scale Integr. Syst.
Yinhe Han, Jianbo Dong, Kaiheng Weng, Ying Wang, Xiaowei Li
2016 J jnl
PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM.
IEEE Trans. Very Large Scale Integr. Syst.
Ying Wang, Yinhe Han, Huawei Li, Lei Zhang, Yuanqing Cheng, Xiaowei Li
2016 — conf
PowerCap: Leverage Performance-Equivalent Resource Configurations for power capping.
IGSC
Faqiang Sun, Huawei Li, Yinhe Han, Guihai Yan, Jun Ma
2016 J jnl
Statistical energy optimization on voltage-frequency island based MPSoCs in the presence of process variations.
Microelectron. J.
Song Jin, Yinhe Han, Songwei Pei
2016 J jnl
VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache.
IEEE Trans. Very Large Scale Integr. Syst.
Ying Wang, Yinhe Han, Huawei Li, Xiaowei Li
2016 J jnl
Wide Operational Range Processor Power Delivery Design for Both Super-Threshold Voltage and Near-Threshold Voltage Computing.
J. Comput. Sci. Technol.
Xin He, Guihai Yan, Yinhe Han, Xiaowei Li
2015 C conf
A case of precision-tunable STT-RAM memory design for approximate neural network.
ISCAS
Ying Wang, Lili Song, Yinhe Han, Yuanqing Cheng, Huawei Li, Xiaowei Li
2015 J jnl
A signal degradation reduction method for memristor ratioed logic (MRL) gates.
IEICE Electron. Express
Bosheng Liu, Ying Wang, Zhiqiang You, Yinhe Han, Xiaowei Li
2015 J jnl
Data Remapping for Static NUCA in Degradable Chip Multiprocessors.
IEEE Trans. Very Large Scale Integr. Syst.
Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li
2015 J jnl
Economizing TSV Resources in 3-D Network-on-Chip Design.
IEEE Trans. Very Large Scale Integr. Syst.
Ying Wang, Yinhe Han, Lei Zhang, Binzhang Fu, Cheng Liu, Huawei Li, Xiaowei Li
2015 — conf
On optimizing system energy of multi-core SoCs based on dynamically reconfigurable voltage-frequency island.
VLSI-DAT
Song Jin, Songwei Pei, Yinhe Han, Huawei Li
2015 A* conf
ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing.
DAC
Ying Wang, Yinhe Han, Lei Zhang, Huawei Li, Xiaowei Li
2015 J jnl
RISO: Enforce Noninterfered Performance With Relaxed Network-on-Chip Isolation in Many-Core Cloud Processors.
IEEE Trans. Very Large Scale Integr. Syst.
Hang Lu, Binzhang Fu, Ying Wang, Yinhe Han, Guihai Yan, Xiaowei Li
2015 — conf
ShuttleNoC: Boosting on-chip communication efficiency by enabling localized power adaptation.
ASP-DAC
Hang Lu, Guihai Yan, Yinhe Han, Ying Wang, Xiaowei Li
2014 J jnl
A General-Purpose Many-Accelerator Architecture Based on Dataflow Graph Clustering of Applications.
J. Comput. Sci. Technol.
Peng Chen, Lei Zhang, Yinhe Han, Yunji Chen
2014 — conf
A low power DRAM refresh control scheme for 3D memory cube.
COOL Chips
Ying Wang, Yinhe Han, Huawei Li
2014 — conf
Amphisbaena: Modeling two orthogonal ways to hunt on heterogeneous many-cores.
ASP-DAC
Jun Ma, Guihai Yan, Yinhe Han, Xiaowei Li
2014 A conf
Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cube.
ICCAD
Yinhe Han, Ying Wang, Huawei Li, Xiaowei Li
2014 J jnl
Reinventing Memory System Design for Many-Accelerator Architecture.
J. Comput. Sci. Technol.
Ying Wang, Lei Zhang, Yinhe Han, Huawei Li
2014 J jnl
SmartCap: Using Machine Learning for Power Adaptation of Smartphone's Application Processor.
ACM Trans. Design Autom. Electr. Syst.
Xueliang Li, Guihai Yan, Yinhe Han, Xiaowei Li
2014 A conf
SuperRange: Wide operational range power delivery design for both STV and NTV computing.
DATE
Xin He, Guihai Yan, Yinhe Han, Xiaowei Li
2014 J jnl
Test-Quality Optimization for Variable $n$ -Detections of Transition Faults.
IEEE Trans. Very Large Scale Integr. Syst.
Dawen Xu, Huawei Li, Amirali Ghofrani, Kwang-Ting Cheng, Yinhe Han, Xiaowei Li
2014 — conf
Variation-aware statistical energy optimization on voltage-frequency island based MPSoCs under performance yield constraints.
ASP-DAC
Song Jin, Yinhe Han, Songwei Pei
2014 J jnl
ZoneDefense: A Fault-Tolerant Routing for 2-D Meshes Without Virtual Channels.
IEEE Trans. Very Large Scale Integr. Syst.
Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li
2013 C conf
Enabling Near-Threshold Voltage(NTV) operation in Multi-VDD cache for power reduction.
ISCAS
Yinhe Han, Ying Wang, Huawei Li, Xiaowei Li
2013 — conf
On predicting NBTI-induced circuit aging by isolating leakage change.
ISQED
Yinhe Han, Song Jin, Jibing Qiu, Qiang Xu, Xiaowei Li
2013 A* conf
RISO: relaxed network-on-chip isolation for cloud processors.
DAC
Hang Lu, Guihai Yan, Yinhe Han, Binzhang Fu, Xiaowei Li
2013 J jnl
RevivePath: Resilient Network-on-Chip Design Through Data Path Salvaging of Router.
J. Comput. Sci. Technol.
Yinhe Han, Cheng Liu, Hang Lu, Wen-Bo Li, Lei Zhang, Xiaowei Li
2013 A conf
SmartCap: user experience-oriented power adaptation for smartphone's application processor.
DATE
Xueliang Li, Guihai Yan, Yinhe Han, Xiaowei Li
2013 J jnl
TSV Minimization for Circuit - Partitioned 3D SoC Test Wrapper Design.
J. Comput. Sci. Technol.
Yuanqing Cheng, Lei Zhang, Yinhe Han, Xiaowei Li
2013 J jnl
Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs.
IEEE Trans. Very Large Scale Integr. Syst.
Yuanqing Cheng, Lei Zhang, Yinhe Han, Xiaowei Li
2013 J jnl
Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction.
IEEE Trans. Very Large Scale Integr. Syst.
Song Jin, Yinhe Han, Huawei Li, Xiaowei Li
2012 A conf
A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems.
DATE
Jianliang Gao, Jianxin Wang, Yinhe Han, Lei Zhang, Xiaowei Li
2012 A* conf
AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture.
HPCA
Guihai Yan, Yingmin Li, Yinhe Han, Xiaowei Li, Minyi Guo, Xiaoyao Liang
2012 J jnl
M-IVC: Applying multiple input vectors to co-optimize aging and leakage.
Microelectron. J.
Song Jin, Yinhe Han
2011 J jnl
A New Multiple-Round Dimension-Order Routing for Networks-on-Chip.
IEICE Trans. Inf. Syst.
Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li
2011 — conf
A resilient on-chip router design through data path salvaging.
ASP-DAC
Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li
2011 A* conf
An abacus turn model for time/space-efficient reconfigurable routing.
ISCA
Binzhang Fu, Yinhe Han, Jun Ma, Huawei Li, Xiaowei Li
2011 A conf
Eliminating data invalidation in debugging multiple-clock chips.
DATE
Jianliang Gao, Yinhe Han, Xiaowei Li
2011 A conf
Flex memory: Exploiting and managing abundant off-chip optical bandwidth.
DATE
Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li
2011 J jnl
MicroFix: Using timing interpolation and delay sensors for power reduction.
ACM Trans. Design Autom. Electr. Syst.
Guihai Yan, Yinhe Han, Hui Liu, Xiaoyao Liang, Xiaowei Li
2011 J jnl
ReviveNet: A Self-Adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation.
IEEE Trans. Computers
Guihai Yan, Yinhe Han, Xiaowei Li
2011 J jnl
SVFD: A Versatile Online Fault Detection Scheme via Checking of Stability Violation.
IEEE Trans. Very Large Scale Integr. Syst.
Guihai Yan, Yinhe Han, Xiaowei Li
2011 J jnl
Statistical lifetime reliability optimization considering joint effect of process variation and aging.
Integr.
Song Jin, Yinhe Han, Huawei Li, Xiaowei Li
2011 — conf
Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip.
ASP-DAC
Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li
2011 A* conf
Wear rate leveling: lifetime enhancement of PRAM with endurance variation.
DAC
Jianbo Dong, Lei Zhang, Yinhe Han, Ying Wang, Xiaowei Li
2011 — conf
Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC.
Asian Test Symposium
Yuanqing Cheng, Lei Zhang, Yinhe Han, Jun Liu, Xiaowei Li
2010 J jnl
A Novel Post-Silicon Debug Mechanism Based on Suspect Window.
IEICE Trans. Inf. Syst.
Jianliang Gao, Yinhe Han, Xiaowei Li
2010 A conf
Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs.
DATE
Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li
2010 C conf
Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors.
PRDC
Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li
2010 J jnl
Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power.
IEICE Trans. Inf. Syst.
Jun Liu, Yinhe Han, Xiaowei Li
2010 A* conf
Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors.
ISCA
Guihai Yan, Xiaoyao Liang, Yinhe Han, Xiaowei Li
2010 — conf
P^(2)CLRAF: An Pre- and Post-Silicon Cooperated Circuit Lifetime Reliability Analysis Framework.
Asian Test Symposium
Song Jin, Yinhe Han, Huawei Li, Xiaowei Li
2010 J jnl
Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling.
J. Syst. Archit.
Jianbo Dong, Lei Zhang, Yinhe Han, Guihai Yan, Xiaowei Li
2010 A conf
Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors.
DATE
Lei Zhang, Yue Yu, Jianbo Dong, Yinhe Han, Shangping Ren, Xiaowei Li
2010 A conf
nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications.
ITC
Huawei Li, Dawen Xu, Yinhe Han, Kwang-Ting Cheng, Xiaowei Li
2009 C conf
A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes.
PRDC
Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li
2009 Misc conf
A New Post-Silicon Debug Approach Based on Suspect Window.
VTS
Jianliang Gao, Yinhe Han, Xiaowei Li
2009 — conf
A Scalable Scan Architecture for Godson-3 Multicore Microprocessor.
Asian Test Symposium
Zichu Qi, Hui Liu, Xiangku Li, Da Wang, Yinhe Han, Huawei Li, Weiwu Hu
2009 A conf
A unified online Fault Detection scheme via checking of Stability Violation.
DATE
Guihai Yan, Yinhe Han, Xiaowei Li
2009 — conf
Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power.
Asian Test Symposium
Jun Liu, Yinhe Han, Xiaowei Li
2009 — conf
M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay.
Asian Test Symposium
Song Jin, Yinhe Han, Lei Zhang, Huawei Li, Xiaowei Li, Guihai Yan
2009 A conf
MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency.
ISLPED
Guihai Yan, Yinhe Han, Hui Liu, Xiaoyao Liang, Xiaowei Li
2009 J jnl
On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Lei Zhang, Yinhe Han, Qiang Xu, Xiaowei Li, Huawei Li
2009 C conf
Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy.
PRDC
Jianbo Dong, Lei Zhang, Yinhe Han, Guihai Yan, Xiaowei Li
2008 J jnl
BAT: Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Asynchronous Transmission.
IEICE Trans. Electron.
Guihai Yan, Yinhe Han, Xiaowei Li, Hui Liu
2008 A conf
Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology.
DATE
Lei Zhang, Yinhe Han, Qiang Xu, Xiaowei Li
2007 J jnl
Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit.
IEEE Trans. Very Large Scale Integr. Syst.
Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra
2007 — conf
Frequency Analysis Method for Propagation of Transient Errors in Combinational Logic.
ATS
Shaohua Lei, Yinhe Han, Xiaowei Li
2007 J jnl
Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment.
J. Comput. Sci. Technol.
Wei Wang, Yu Hu, Yinhe Han, Xiaowei Li, You-Sheng Zhang
2006 C conf
An on-chip combinational decompressor for reducing test data volume.
ISCAS
Jie Don, Yu Hu, Yinhe Han, Xiaowei Li
2006 J jnl
Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time.
IEICE Trans. Inf. Syst.
Yu Hu, Yinhe Han, Xiaowei Li, Huawei Li, Xiaoqing Wen
2006 J jnl
Embedded test resource for SoC to reduce required tester channels based on advanced convolutional codes.
IEEE Trans. Instrum. Meas.
Yinhe Han, Xiaowei Li, Huawei Li, Anshuman Chandra
2006 B conf
Fast Packet Classification using Group Bit Vector.
GLOBECOM
Tong Liu, Huawei Li, Xiaowei Li, Yinhe Han
2006 J jnl
Response compaction for system-on-a-chip based on advanced convolutional codes.
Sci. China Ser. F Inf. Sci.
Yinhe Han, Huawei Li, Xiaowei Li, Anshuman Chandra
2006 — conf
Test data compression based on clustered random access scan.
ATS
Yu Hu, Cheng Li, Jia Li, Yinhe Han, Xiaowei Li, Wei Wang, Huawei Li, Laung-Terng Wang, Xiaoqing Wen
2005 — conf
Deterministic and low power BIST based on scan slice overlapping.
ISCAS (6)
Ji Li, Yinhe Han, Xiaowei Li
2005 — conf
Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor.
Asian Test Symposium
Yinhe Han, Xiaowei Li, Shivakumar Swaminathan, Yu Hu, Anshuman Chandra
2005 — conf
SoC Leakage Power Reduction Algorithm by Input Vector Control.
SoC
Xiaotao Chang, Dongrui Fan, Yinhe Han, Zhimin Zhang
2005 J jnl
Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction.
J. Comput. Sci. Technol.
Yinhe Han, Xiaowei Li, Huawei Li, Anshuman Chandra
2005 — conf
Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code.
ASP-DAC
Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li
2005 — conf
Using MUXs Network to Hide Bunches of Scan Chains.
ISQED
Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li
2005 — conf
Validation analysis and test flow optimization of VLSI chip.
ISCAS (6)
Yanzhuo Tan, Yinhe Han, Xiaowei Li, Feiyin Lu, Yuchuan Chen
2005 J jnl
Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores.
IEICE Trans. Inf. Syst.
Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra, Xiaoqing Wen
2004 — conf
Pair Balance-Based Test Scheduling for SOCs.
Asian Test Symposium
Yu Hu, Yinhe Han, Huawei Li, Tao Lv, Xiaowei Li
2004 — conf
Rapid and Energy-Efficient Testing for Embedded Cores.
Asian Test Symposium
Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra
2004 — conf
Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes.
DFT
Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra
2004 — conf
Simultaneous Reduction of Test Data Volume and Testing Power for Scan-Based Test.
ESA/VLSI
Yinhe Han, Xiaowei Li
2003 — conf
Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste.
Asian Test Symposium
Yinhe Han, Yongjun Xu, Huawei Li, Xiaowei Li, Anshuman Chandra