Yingke Gao

13 papers B 1C 2Misc 3Journal 1Unranked 6
YearRankTypeTitle / Venue / Authors
2025 C conf
An FPGA-based Real-Time Optical Flow Accelerator for Recurrent All-Pairs Field Transforms.
ISCAS
Xiaoliang Jia, Hong Tang, Xiqin Zheng, Yingke Gao, Longjun Liu
2025 Misc conf
D2S: Towards Efficient Sparse 3D Object Detection via Dense to Sparse Knowledge Distillation.
ICASSP
Yuqi Huang, Longjun Liu, Yingke Gao, Haonan Zhang, Haoteng Li
2024 J jnl
Approximate data mapping in refresh-free DRAM for energy-efficient computing in modern mobile systems.
Comput. Commun.
Sen Li, Hui Jin, Yingke Gao, Ying Wang, Shuhong Dai, Yongjun Xu, Long Cheng
2023 B conf
Cross-Layer Patch Alignment and Intra-and-Inter Patch Relations for Knowledge Distillation.
ICIP
Yi Zhang, Yingke Gao, Haonan Zhang, Xinyu Lei, Longjun Liu
2023 — conf
Design and Reliability Analysis of Spaceborne Microsystem SiP.
EEET
Zheng Yang, Ruohan Zu, Shenglong Li, Yongcong Yang, Yingke Gao
2017 Misc conf
Flip-flop clustering based trace signal selection for post-silicon debug.
VTS
Yun Cheng, Huawei Li, Ying Wang, Yingke Gao, Bo Liu, Xiaowei Li
2016 Misc conf
Path constraint solving based test generation for observability-enhanced branch coverage.
VTS
Yanhong Zhou, Huawei Li, Tiancheng Wang, Bo Liu, Yingke Gao, Xiaowei Li
2016 — conf
Property Coverage Analysis Based Trustworthiness Verification for Potential Threats from EDA Tools.
ATS
Yingxin Qiu, Huawei Li, Tiancheng Wang, Bo Liu, Yingke Gao, Xiaowei Li
2013 — conf
A design of configurable image enhancement unit.
ASICON
Zhiyuan Xue, Huan Ying, Yingke Gao, Tiejun Zhang, Donghui Wang, Chaohuan Hou
2013 — conf
Design and implementation of a dynamic loop buffer by reusing the instruction buffer.
ASICON
Qi Wang, Yingke Gao, Donghui Wang, Tiejun Zhang, Chaohuan Hou
2013 — conf
Design and implementation of transaction level processor based on UVM.
ASICON
Yingke Gao, Diancheng Wu, Quanquan Li, Tiejun Zhang, Chaohuan Hou
2013 C conf
Design of Bitstream Co-processor for Multimedia Applications.
DASC
Yingke Gao, Huan Ying, Zhiyuan Xue, Tiejun Zhang, Donghui Wang, Chaohuan Hou
2011 — conf
A test approach of combining partial scan with functional testing for high performance processors.
ASICON
Quanquan Li, Yingke Gao, Tiejun Zhang, Chaohuan Hou