Yingjie Qi

38 papers A* 7A 1C 1Journal 26Unranked 3
YearRankTypeTitle / Venue / Authors
2026 J jnl
ACE-GNN: Adaptive GNN Co-Inference With System-Aware Scheduling in Dynamic Edge Environments.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Xinming Wei, Cenlin Duan, Weisheng Zhao, Chunming Hu
2026 J jnl
CIMinus: Empowering Sparse DNN Workloads Modeling and Exploration on SRAM-Based CIM Architectures.
IEEE Trans. Computers
Yingjie Qi, Jianlei Yang, Rubing Yang, Cenlin Duan, Xiaolin He, Ziyan He, Weitao Pan, Weisheng Zhao
2026 J jnl
Efficient SRAM-PIM Co-Design by Joint Exploration of Value-Level and Bit-Level Sparsity.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Cenlin Duan, Jianlei Yang, Yikun Wang, Yiou Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao
2026 J jnl
GCoDE: Efficient Device-Edge Co-Inference for GNNs via Architecture-Mapping Co-Search.
IEEE Trans. Computers
Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Zhi Yang, Weisheng Zhao, Chunming Hu
2026 — conf
MIREDO: MIP-Driven Resource-Efficient Dataflow Optimization for Computing-in-Memory Accelerator.
ASP-DAC
Xiaolin He, Cenlin Duan, Yingjie Qi, Xiao May, Jianlei Yang
2025 J jnl
ACE-GNN: Adaptive GNN Co-Inference with System-Aware Scheduling in Dynamic Edge Environments.
CoRR
Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Xinming Wei, Cenlin Duan, Weisheng Zhao, Chunming Hu
2025 A* conf
CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures.
DAC
Yingjie Qi, Jianlei Yang, Yiou Wang, Yikun Wang, Dayu Wang, Ling Tang, Cenlin Duan, Xiaolin He, Weisheng Zhao
2025 J jnl
CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures.
CoRR
Yingjie Qi, Jianlei Yang, Yiou Wang, Yikun Wang, Dayu Wang, Ling Tang, Cenlin Duan, Xiaolin He, Weisheng Zhao
2025 J jnl
CIMinus: Empowering Sparse DNN Workloads Modeling and Exploration on SRAM-based CIM Architectures.
CoRR
Yingjie Qi, Jianlei Yang, Rubing Yang, Cenlin Duan, Xiaolin He, Ziyan He, Weitao Pan, Weisheng Zhao
2025 J jnl
Efficient SRAM-PIM Co-design by Joint Exploration of Value-Level and Bit-Level Sparsity.
CoRR
Cenlin Duan, Jianlei Yang, Yikun Wang, Yiou Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao
2025 J jnl
GCoDE: Efficient Device-Edge Co-Inference for GNNs via Architecture-Mapping Co-Search.
CoRR
Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Zhi Yang, Weisheng Zhao, Chunming Hu
2025 J jnl
HPIM: Heterogeneous Processing-In-Memory-based Accelerator for Large Language Models Inference.
CoRR
Cenlin Duan, Jianlei Yang, Rubing Yang, Yikun Wang, Yiou Wang, Lingkun Long, Yingjie Qi, Xiaolin He, Ao Zhou, Xueyan Wang, Weisheng Zhao
2025 J jnl
MIREDO: MIP-Driven Resource-Efficient Dataflow Optimization for Computing-in-Memory Accelerator.
CoRR
Xiaolin He, Cenlin Duan, Yingjie Qi, Xiao Ma, Jianlei Yang
2025 C conf
Towards Affordable, Adaptive and Automatic GNN Training on CPU-GPU Heterogeneous Platforms.
ICCD
Tong Qiao, Ao Zhou, Yingjie Qi, Yiou Wang, Han Wan, Jianlei Yang, Chunming Hu
2025 J jnl
Towards Affordable, Adaptive and Automatic GNN Training on CPU-GPU Heterogeneous Platforms.
CoRR
Tong Qiao, Ao Zhou, Yingjie Qi, Yiou Wang, Han Wan, Jianlei Yang, Chunming Hu
2024 J jnl
Architectural Implications of GNN Aggregation Programming Abstractions.
IEEE Comput. Archit. Lett.
Yingjie Qi, Jianlei Yang, Ao Zhou, Tong Qiao, Chunming Hu
2024 J jnl
DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Cenlin Duan, Jianlei Yang, Xiaolin He, Yingjie Qi, Yikun Wang, Yiou Wang, Ziyan He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weitao Pan, Weisheng Zhao
2024 A* conf
GNNavigator: Towards Adaptive Training of Graph Neural Networks via Automatic Guideline Exploration.
DAC
Tong Qiao, Jianlei Yang, Yingjie Qi, Ao Zhou, Chen Bai, Bei Yu, Weisheng Zhao, Chunming Hu
2024 J jnl
GNNavigator: Towards Adaptive Training of Graph Neural Networks via Automatic Guideline Exploration.
CoRR
Tong Qiao, Jianlei Yang, Yingjie Qi, Ao Zhou, Chen Bai, Bei Yu, Weisheng Zhao, Chunming Hu
2024 A* conf
Graph Neural Networks Automated Design and Deployment on Device-Edge Co-Inference Systems.
DAC
Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Zhi Yang, Weisheng Zhao, Chunming Hu
2024 J jnl
Graph Neural Networks Automated Design and Deployment on Device-Edge Co-Inference Systems.
CoRR
Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Zhi Yang, Weisheng Zhao, Chunming Hu
2024 J jnl
HGNAS: Hardware-Aware Graph Neural Architecture Search for Edge Devices.
CoRR
Ao Zhou, Jianlei Yang, Yingjie Qi, Tong Qiao, Yumeng Shi, Cenlin Duan, Weisheng Zhao, Chunming Hu
2024 J jnl
HGNAS: Hardware-Aware Graph Neural Architecture Search for Edge Devices.
IEEE Trans. Computers
Ao Zhou, Jianlei Yang, Yingjie Qi, Tong Qiao, Yumeng Shi, Cenlin Duan, Weisheng Zhao, Chunming Hu
2024 A* conf
Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity.
DAC
Cenlin Duan, Jianlei Yang, Yiou Wang, Yikun Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao
2024 J jnl
Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity.
CoRR
Cenlin Duan, Jianlei Yang, Yiou Wang, Yikun Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao
2023 J jnl
Architectural Implications of GNN Aggregation Programming Abstractions.
CoRR
Yingjie Qi, Jianlei Yang, Ao Zhou, Tong Qiao, Chunming Hu
2023 J jnl
DDC-PIM: Efficient Algorithm/Architecture Co-design for Doubling Data Capacity of SRAM-based Processing-In-Memory.
CoRR
Cenlin Duan, Jianlei Yang, Xiaolin He, Yingjie Qi, Yikun Wang, Yiou Wang, Ziyan He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weitao Pan, Weisheng Zhao
2023 A* conf
Hardware-Aware Graph Neural Network Automated Design for Edge Computing Platforms.
DAC
Ao Zhou, Jianlei Yang, Yingjie Qi, Yumeng Shi, Tong Qiao, Weisheng Zhao, Chunming Hu
2023 J jnl
Hardware-Aware Graph Neural Network Automated Design for Edge Computing Platforms.
CoRR
Ao Zhou, Jianlei Yang, Yingjie Qi, Yumeng Shi, Tong Qiao, Weisheng Zhao, Chunming Hu
2022 J jnl
Eventor: An Efficient Event-Based Monocular Multi-View Stereo Accelerator on FPGA Platform.
CoRR
Mingjun Li, Jianlei Yang, Yingjie Qi, Meng Dong, Yuhao Yang, Runze Liu, Weitao Pan, Bei Yu, Weisheng Zhao
2022 A* conf
Eventor: an efficient event-based monocular multi-view stereo accelerator on FPGA platform.
DAC
Mingjun Li, Jianlei Yang, Yingjie Qi, Meng Dong, Yuhao Yang, Runze Liu, Weitao Pan, Bei Yu, Weisheng Zhao
2021 A conf
Brief Industry Paper: optimizing Memory Efficiency of Graph Neural Networks on Edge Computing Platforms.
RTAS
Ao Zhou, Jianlei Yang, Yeqi Gao, Tong Qiao, Yingjie Qi, Xiaoyi Wang, Yunli Chen, Pengcheng Dai, Weisheng Zhao, Chunming Hu
2021 J jnl
Optimizing Memory Efficiency of Graph Neural Networks on Edge Computing Platforms.
CoRR
Ao Zhou, Jianlei Yang, Yeqi Gao, Tong Qiao, Yingjie Qi, Xiaoyi Wang, Yunli Chen, Pengcheng Dai, Weisheng Zhao, Chunming Hu
2021 J jnl
Rapid analysis and detection algorithm and prevention countermeasures of urban traffic accidents under artificial intelligence.
Int. J. Grid Util. Comput.
Zhao Yang, Yingjie Qi
2020 — conf
Accelerating CNN Training by Pruning Activation Gradients.
ECCV (25)
Xucheng Ye, Pengcheng Dai, Junyu Luo, Xin Guo, Yingjie Qi, Jianlei Yang, Yiran Chen
2020 A* conf
TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture.
DAC
Xueyan Wang, Jianlei Yang, Yinglin Zhao, Yingjie Qi, Meichen Liu, Xingzhou Cheng, Xiaotao Jia, Xiaoming Chen, Gang Qu, Weisheng Zhao
2020 J jnl
TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture.
CoRR
Xueyan Wang, Jianlei Yang, Yinglin Zhao, Yingjie Qi, Meichen Liu, Xingzhou Cheng, Xiaotao Jia, Xiaoming Chen, Gang Qu, Weisheng Zhao
2008 — conf
Utility-based adaptive multi-frame iterative algorithm for resource scheduling in OFDMA networks.
ICT
Zongrui Ding, Guopeng Ding, Yingjie Qi, Limin Xiao, Jing Wang