Ying-Zu Lin

21 papers B 2Journal 11Unranked 8
YearRankTypeTitle / Venue / Authors
2022 B conf
Using deep learning models to predict student performance in introductory computer programming courses.
ICALT
Yueh-hui Vanessa Chiang, Ying-Zu Lin, Nian-Shing Chen
2021 — conf
An 80MHz-BW 640MS/s Time-Interleaved Passive Noise- Shaping SAR ADC in 22nm FDSOI Process.
ISSCC
Chin-Yu Lin, Ying-Zu Lin, Chih-Hou Tsai, Chao-Hsin Lu
2021 B conf
An investigation of group, rater and ratee effects on peer-/self-assessments in a collaborative learning environment in higher education: a cross-classified multilevel analysis.
ICALT
Yueh-hui Vanessa Chiang, Ying-Zu Lin, Nian-Shing Chen
2019 — conf
A 40MHz-BW 320MS/s Passive Noise-Shaping SAR ADC With Passive Signal-Residue Summation in 14nm FinFET.
ISSCC
Ying-Zu Lin, Chin-Yu Lin, Shan-Chih Tsou, Chih-Hou Tsai, Chao-Hsin Lu
2016 — conf
A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with fast reference charge neutralization and background timing-skew calibration in 16-nm CMOS.
VLSI Circuits
Ying-Zu Lin, Chih-Hou Tsai, Shan-Chih Tsou, Chao-Hsin Lu
2015 J jnl
A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS.
IEEE J. Solid State Circuits
Chun-Cheng Liu, Che-Hsun Kuo, Ying-Zu Lin
2014 — conf
A 10b 100kS/s SAR ADC with charge recycling switching method.
A-SSCC
Kai-Hsiang Chiang, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin
2013 J jnl
10-bit 30-MS/s SAR ADC Using a Switchback Switching Method.
IEEE Trans. Very Large Scale Integr. Syst.
Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu, Ying-Zu Lin
2013 J jnl
A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ying-Zu Lin, Chun-Cheng Liu, Guan-Ying Huang, Ya-Ting Shyu, Yen-Ting Liu, Soon-Jyh Chang
2013 J jnl
Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops.
IEEE Trans. Very Large Scale Integr. Syst.
Ya-Ting Shyu, Jai-Ming Lin, Chun-Po Huang, Cheng-Wu Lin, Ying-Zu Lin, Soon-Jyh Chang
2012 J jnl
A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications.
IEEE J. Solid State Circuits
Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu, Ying-Zu Lin
2012 J jnl
A Low-Cost Bit-Error-Rate BIST Circuit for High-Speed ADCs Based on Gray Coding.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Ya-Ting Shyu, Ying-Zu Lin, Rong-Sing Chu, Guan-Ying Huang, Soon-Jyh Chang
2011 — conf
A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS.
A-SSCC
Ying-Zu Lin, Soon-Jyh Chang, Ya-Ting Shyu, Guan-Ying Huang, Chun-Cheng Liu
2010 J jnl
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure.
IEEE J. Solid State Circuits
Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin
2010 — conf
A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation.
ISSCC
Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin, Chung-Ming Huang, Chih-Hao Huang, Linkai Bu, Chih-Chung Tsai
2010 J jnl
A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme.
IEEE Trans. Very Large Scale Integr. Syst.
Ying-Zu Lin, Cheng-Wu Lin, Soon-Jyh Chang
2010 J jnl
An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu, Guan-Ying Huang
2009 J jnl
A 5-bit 4.2-GS/s Flash ADC in 0.13-µm CMOS Process.
IEICE Trans. Electron.
Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu
2009 — conf
A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS.
ISSCC
Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu, Guan-Ying Huang
2008 J jnl
A Digitally Calibrated CMOS Transconductor With a 100-MHz Bandwidth and 75-dB SFDR.
IEEE Trans. Circuits Syst. II Express Briefs
Soon-Jyh Chang, Ying-Zu Lin, Yen-Ting Liu
2007 — conf
A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS.
CICC
Ying-Zu Lin, Yen-Ting Liu, Soon-Jyh Chang