Yin-Nien Chen

17 papers A 1C 4Journal 4Unranked 8
YearRankTypeTitle / Venue / Authors
2017 C conf
Exploration and evaluation of low-dropout linear voltage regulator with FinFET, TFET and hybrid TFET-FinFET implementations.
ISCAS
Chia-Ning Chang, Yin-Nien Chen, Po-Tsang Huang, Pin Su, Ching-Te Chuang
2016 — conf
Exploration and evaluation of hybrid TFET-MOSFET monolithic 3D SRAMs considering interlayer coupling.
ICICDT
Jian-Hao Wang, Yin-Nien Chen, Pin Su, Ching-Te Chuang
2015 — conf
Evaluation of 32-Bit carry-look-ahead adder circuit with hybrid tunneling FET and FinFET devices.
ICICDT
Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2015 C conf
Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness.
ISCAS
Chien-Ju Chen, Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2015 — conf
Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications.
SoCC
Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2014 J jnl
Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2014 J jnl
Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2014 C conf
Investigation and optimization of monolithic 3D logic circuits and SRAM cells considering interlayer coupling.
ISCAS
Ming-Long Fan, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang
2014 J jnl
Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits.
Microelectron. Reliab.
Ming-Long Fan, Shao-Yu Yang, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang
2014 A conf
Ultra-low voltage mixed TFET-MOSFET 8T SRAM cell.
ISLPED
Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2013 — conf
Impacts of single trap induced random telegraph noise on Si and Ge nanowire FETs, 6T SRAM cells and logic circuits.
ICICDT
Shao-Yu Yang, Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2012 — conf
A comparative analysis of tunneling FET circuit switching characteristics and SRAM stability and performance.
ESSDERC
Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Ming-Fu Tsai, Chia-Hao Pao, Pin Su, Ching-Te Chuang
2012 — conf
A comprehensive comparative analysis of FinFET and Trigate device, SRAM and logic circuits.
APCCAS
Chia-Hao Pao, Ming-Long Fan, Ming-Fu Tsai, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2012 C conf
High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder.
ISCAS
Hao-I Yang, Yi-Wei Lin, Mao-Chih Hsia, Geng-Cing Lin, Chi-Shin Chang, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu
2012 — conf
Impacts of random telegraph noise on the analog properties of FinFET and trigate devices and Widlar current source.
ICICDT
Chia-Hao Pao, Ming-Long Fan, Ming-Fu Tsai, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
2012 J jnl
Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Ming-Long Fan, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang
2011 — conf
A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control.
SoCC
Hao-I Yang, Shih-Chi Yang, Mao-Chih Hsia, Yung-Wei Lin, Yi-Wei Lin, Chien-Hen Chen, Chi-Shin Chang, Geng-Cing Lin, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu