Yijin Guan

23 papers A* 2A 1B 1Misc 1Journal 11Unranked 7
YearRankTypeTitle / Venue / Authors
2025 — conf
CTXNL: A Software-Hardware Co-designed Solution for Efficient CXL-Based Transaction Processing.
ASPLOS (2)
Zhao Wang, Yiqi Chen, Cong Li, Yijin Guan, Dimin Niu, Tianchan Guan, Zhaoyang Du, Xingda Wei, Guangyu Sun
2025 J jnl
MemTunnel: A CXL-Based Rack-Scale Host Memory Pooling Architecture for Cloud Service.
IEEE Trans. Parallel Distributed Syst.
Tianchan Guan, Yijin Guan, Zhaoyang Du, Jiacheng Ma, Boyu Tian, Zhao Wang, Teng Ma, Zheng Liu, Yang Kong, Yuan Xie, Mingyu Gao, Guangyu Sun, Hongzhong Zheng, Dimin Niu
2024 — conf
HydraRPC: RPC in the CXL Era.
USENIX ATC
Teng Ma, Zheng Liu, Chengkun Wei, Jialiang Huang, Youwei Zhuo, Haoyu Li, Ning Zhang, Yijin Guan, Dimin Niu, Mingxing Zhang, Tao Ma
2024 — conf
Salus: A Practical Trusted Execution Environment for CPU-FPGA Heterogeneous Cloud Platforms.
ASPLOS (4)
Yu Zou, Yiran Li, Sheng Wang, Le Su, Zhen Gu, Yanheng Lu, Yijin Guan, Dimin Niu, Mingyu Gao, Yuan Xie, Feifei Li
2022 — conf
184QPS/W 64Mb/mm
ISSCC
Dimin Niu, Shuangchen Li, Yuhao Wang, Wei Han, Zhe Zhang, Yijin Guan, Tianchan Guan, Fei Sun, Fei Xue, Lide Duan, Yuanwei Fang, Hongzhong Zheng, Xiping Jiang, Song Wang, Fengguo Zuo, Yubing Wang, Bing Yu, Qiwei Ren, Yuan Xie
2022 J jnl
Accelerating CPU-Based Sparse General Matrix Multiplication With Binary Row Merging.
IEEE Access
Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Hongzhong Zheng, Yuan Xie
2022 J jnl
Accelerating CPU-based Sparse General Matrix Multiplication with Binary Row Merging.
CoRR
Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Hongzhong Zheng, Yuan Xie
2022 J jnl
Flatfish: A Reinforcement Learning Approach for Application-Aware Address Mapping.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xingchen Li, Zhihang Yuan, Yijin Guan, Guangyu Sun, Tao Zhang, Rongshan Wei, Dimin Niu
2022 A* conf
Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network.
ISCA
Shuangchen Li, Dimin Niu, Yuhao Wang, Wei Han, Zhe Zhang, Tianchan Guan, Yijin Guan, Heng Liu, Linyong Huang, Zhaoyang Du, Fei Xue, Yuanwei Fang, Hongzhong Zheng, Yuan Xie
2022 J jnl
OpSparse: A Highly Optimized Framework for Sparse General Matrix Multiplication on GPUs.
IEEE Access
Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Linyong Huang, Hongzhong Zheng, Yuan Xie
2022 J jnl
OpSparse: a Highly Optimized Framework for Sparse General Matrix Multiplication on GPUs.
CoRR
Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Linyong Huang, Hongzhong Zheng, Yuan Xie
2022 J jnl
PIMulator-NN: An Event-Driven, Cross-Level Simulation Framework for Processing-In-Memory-Based Neural Network Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Qilin Zheng, Xingchen Li, Yijin Guan, Zongwei Wang, Yimao Cai, Yiran Chen, Guangyu Sun, Ru Huang
2022 J jnl
Practical Near-Data-Processing Architecture for Large-Scale Distributed Graph Neural Network.
IEEE Access
Linyong Huang, Zhe Zhang, Shuangchen Li, Dimin Niu, Yijin Guan, Hongzhong Zheng, Yuan Xie
2022 B conf
Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio.
ICPADS
Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Nianxiong Tan, Xiaopeng Yu, Hongzhong Zheng, Jianyi Meng, Xiaolang Yan, Yuan Xie
2022 J jnl
Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio.
CoRR
Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Nianxiong Tan, Xiaopeng Yu, Hongzhong Zheng, Jianyi Meng, Xiaolang Yan, Yuan Xie
2021 A* conf
BlockGNN: Towards Efficient GNN Acceleration Using Block-Circulant Weight Matrices.
DAC
Zhe Zhou, Bizhao Shi, Zhe Zhang, Yijin Guan, Guangyu Sun, Guojie Luo
2021 J jnl
BlockGNN: Towards Efficient GNN Acceleration Using Block-Circulant Weight Matrices.
CoRR
Zhe Zhou, Bizhao Shi, Zhe Zhang, Yijin Guan, Guangyu Sun, Guojie Luo
2020 J jnl
Crane: Mitigating Accelerator Under-utilization Caused by Sparsity Irregularities in CNNs.
IEEE Trans. Computers
Yijin Guan, Guangyu Sun, Zhihang Yuan, Xingchen Li, Ningyi Xu, Shu Chen, Jason Cong, Yuan Xie
2020 — conf
GNN-PIM: A Processing-in-Memory Architecture for Graph Neural Networks.
ACA
Zhao Wang, Yijin Guan, Guangyu Sun, Dimin Niu, Yuhao Wang, Hongzhong Zheng, Yinhe Han
2017 Misc conf
FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates.
FCCM
Yijin Guan, Hao Liang, Ningyi Xu, Wenqiang Wang, Shaoshuai Shi, Xi Chen, Guangyu Sun, Wei Zhang, Jason Cong
2017 — conf
FPGA-based accelerator for long short-term memory recurrent neural networks.
ASP-DAC
Yijin Guan, Zhihang Yuan, Guangyu Sun, Jason Cong
2017 — conf
Using Data Compression for Optimizing FPGA-Based Convolutional Neural Network Accelerators.
APPT
Yijin Guan, Ningyi Xu, Chen Zhang, Zhihang Yuan, Jason Cong
2015 A conf
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks.
FPGA
Chen Zhang, Peng Li, Guangyu Sun, Yijin Guan, Bingjun Xiao, Jason Cong