Yihe Sun

32 papers A* 2A 5B 1C 1Journal 12Unranked 11
YearRankTypeTitle / Venue / Authors
2024 — conf
Comprehensive identification of corporate financial risk based on Z-score model and F-score model.
ICBAR
Yihe Sun, Zhiqiang Sun, Xueli He, Yangbin Xiang
2024 J jnl
Low/Middle-Frequency Positive External- Damping Design Under Self-Stability Constraint for Inner Control Loop of Grid-Forming Converters.
IEEE Trans. Ind. Electron.
Xiaoqiang Li, Chu Chen, Yihe Sun, Hao Cheng
2013 J jnl
Large-Scale Energy Storage System Design and Optimization for Emerging Electric-Drive Vehicles.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jie Wu, Jia Wang, Kun Li, Hai Zhou, Qin Lv, Li Shang, Yihe Sun
2013 J jnl
On-Chip Systolic Networks for Real-Time Tracking of Pairwise Correlations Between Neurons in a Large-Scale Network.
IEEE Trans. Biomed. Eng.
Bo Yu, Rosa H. M. Chan, Terrence S. T. Mak, Yihe Sun, Chi-Sang Poon
2012 J jnl
Reliability Modeling and Management of Nanophotonic On-Chip Networks.
IEEE Trans. Very Large Scale Integr. Syst.
Zheng Li, Moustafa Mohamed, Xi Chen, Eric Dudley, Ke Meng, Li Shang, Alan Rolf Mickelson, Russ Joseph, Manish Vachharajani, Brian Schwartz, Yihe Sun
2011 — conf
Feasibility study for future implantable neural-silicon interface devices.
EMBC
Allann Al-armaghany, Bo Yu, Terrence S. T. Mak, Kin-Fai Tong, Yihe Sun
2011 J jnl
MOPED: Accelerating Data Communication on Future CMPs.
IEEE Micro
Junli Gu, Yihe Sun, Steven S. Lumetta, Rakesh Kumar
2011 A* conf
MOPED: Orchestrating interprocess message data on CMPs.
HPCA
Junli Gu, Steven S. Lumetta, Rakesh Kumar, Yihe Sun
2011 — conf
Memory efficient on-line streaming for multichannel spike train analysis.
EMBC
Bo Yu, Terrence S. T. Mak, Leslie Smith, Yihe Sun, Alex Yakovlev, Chi-Sang Poon
2011 J jnl
Real-Time FPGA-Based Multichannel Spike Sorting Using Hebbian Eigenfilters.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Bo Yu, Terrence S. T. Mak, Xiangyu Li, Fei Xia, Alexandre Yakovlev, Yihe Sun, Chi-Sang Poon
2011 — conf
Real-time neuronal networks reconstruction using hierarchical systolic arrays.
EMBC
Bo Yu, Terrence S. T. Mak, Yihe Sun, Chi-Sang Poon
2010 B conf
A Reconfigurable Hebbian Eigenfilter for Neurophysiological Spike Train Analysis.
FPL
Bo Yu, Terrence S. T. Mak, Xiangyu Li, Fei Xia, Alexandre Yakovlev, Yihe Sun, Chi-Sang Poon
2010 — conf
Accelerating data movement on future chip multi-processors.
IFMT
Junli Gu, Rakesh Kumar, Steven S. Lumetta, Yihe Sun
2010 J jnl
Global On-Chip Coordination at Light Speed.
IEEE Des. Test Comput.
Zheng Li, Moustafa Mohamed, Hongyu Zhou, Li Shang, Alan Rolf Mickelson, Dejan Filipovic, Manish Vachharajani, Wounjhang Park, Yihe Sun
2010 A conf
Power-efficient variation-aware photonic on-chip network management.
ISLPED
Moustafa Mohamed, Zheng Li, Xi Chen, Li Shang, Alan Rolf Mickelson, Manish Vachharajani, Yihe Sun
2009 J jnl
A Novel Low Energy Scheduling Algorithm for Clustered Very Long Instruction Word Architectures.
J. Low Power Electron.
Yang Xu, Hu He, Yihe Sun
2009 A conf
A high-performance low-power nanophotonic on-chip network.
ISLPED
Zheng Li, Jie Wu, Li Shang, Alan Rolf Mickelson, Manish Vachharajani, Dejan Filipovic, Wounjhang Park, Yihe Sun
2009 A conf
Latency criticality aware on-chip communication.
DATE
Zheng Li, Jie Wu, Li Shang, Robert P. Dick, Yihe Sun
2009 C conf
Simultaneous Multithreading VLIW DSP Architecture with Dynamic Dispatch Mechanism.
DSD
Zheng Shen, Hu He, Yihe Sun
2009 A* conf
Spectrum: a hybrid nanophotonic-electric on-chip network.
DAC
Zheng Li, Dan Fay, Alan Rolf Mickelson, Li Shang, Manish Vachharajani, Dejan Filipovic, Wounjhang Park, Yihe Sun
2008 J jnl
Transaction-Aware Network-on-Chip Resource Reservation.
IEEE Comput. Archit. Lett.
Zheng Li, Changyun Zhu, Li Shang, Robert P. Dick, Yihe Sun
2008 — conf
Using Genetic Evolutionary Software Application Testing to Verify a DSP SoC.
DELTA
Adriel Cheng, Cheng-Chew Lim, Yihe Sun, Hu He, Zhixiong Zhou, Ting Lei
2007 — conf
A 2-Dimension Force-Directed Scheduling Algorithm for Register-File-Connectivity Clustered VLIW Architecture.
ASAP
Zhixiong Zhou, Hu He, Yanjun Zhang, Yihe Sun, Adriel Cheng
2007 J jnl
A Video Specific Instruction Set Architecture for ASIP design.
VLSI Design
Zheng Shen, Hu He, Yanjun Zhang, Yihe Sun
2007 J jnl
Heuristic on a Novel Power Management System Cooperating with Compiler.
J. Low Power Electron.
Yang Xu, Hu He, Zhou Zhixiong, Yanjun Zhang, Yihe Sun
2006 A conf
A Retargetable Compiler of VLIW ASIP for Media Signal Processing.
ESA
Zhou Zhixiong, Yang Xu, He Hu, Yihe Sun
2006 — conf
VS-ISA: A Video Specific Instruction Set Architecture for ASIP Design.
IIH-MSP
Zheng Shen, Hu He, Yanjun Zhang, Yihe Sun
2005 — conf
A new register file access architecture for software pipelining in VLIW processors.
ASP-DAC
Yanjun Zhang, Hu He, Yihe Sun
2003 J jnl
A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems.
J. VLSI Signal Process.
Xingjun Wu, Hongyi Chen, Yihe Sun, Weixin Gai
2003 — conf
Test-Point Selection Algorithm Using Small Signal Model for Scan-Based BIST.
Asian Test Symposium
He Hu, Yihe Sun
2002 — conf
An Optimizing Search Method of Systolic Array Design.
IASTED PDCS
Ke Jiang, Yihe Sun
2001 A conf
Scan array solution for testing power and testing time.
ITC
Lei Xu, Yihe Sun, Hongyi Chen