Yih-Lang Li - RankMe

81 papers A* 10A 17B 2C 2Misc 1Journal 24Unranked 25

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	A Graph-Based Approach for Optimizing Pin Access in Nanosheet FET Standard Cell Library Synthesis. ISPD Meng-Yu Shih, Ting Xin Lin, Yih-Lang Li
2025	A*	`conf`	Reinforcement Learning-Driven Window Selection for Enhanced Window-Based Rip-up and Reroute in Chip Detailed Routing. DAC Yu-Chan Keng, Yu-Chun Pai, Wen-Hao Liu, Haoxing Ren, Danny Liu, Rongjian Liang, Mark Ho, Anthony Agnesina, Yih-Lang Li
2025	—	`conf`	Scalable CFET Cell Library Synthesis with A DRC-Aware Lookup Table to Optimize Valid Pin Access. ISPD Ting-Wei Lee, Ting Xin Lin, Yih-Lang Li
2025	A*	`conf`	Synthesis of CFET Cell Library Leveraging Backside Metal Routing. DAC Ting-Xin Lin, Yih-Lang Li
2024	A*	`conf`	Arbitrary-size Multi-layer OARSMT RL Router Trained with Combinatorial Monte-Carlo Tree Search. DAC Liang-Ting Chen, Hung-Ru Kuo, Yih-Lang Li, Mango C.-T. Chao
2024	—	`conf`	Routability Booster " Synthesize a Routing Friendly Standard Cell Library by Relaxing BEOL Resources. ISPD Bing-Xun Song, Ting Xin Lin, Yih-Lang Li
2023	J	`jnl`	Periodic Physical Activity Information Segmentation, Counting and Recognition From Video. IEEE Access Sheng-Hsien Cheng, Muhammad Atif Sarwar, Yousef-Awwad Daraghmi, Tsì-Uí Ik, Yih-Lang Li
2023	J	`jnl`	Skeleton Based Keyframe Detection Framework for Sports Action Analysis: Badminton Smash Case. IEEE Access Muhammad Atif Sarwar, Yu-Chen Lin, Yousef-Awwad Daraghmi, Tsì-Uí Ik, Yih-Lang Li
2022	—	`conf`	A Reinforcement Learning Agent for Obstacle-Avoiding Rectilinear Steiner Tree Construction. ISPD Po-Yan Chen, Bing-Ting Ke, Tai-Cheng Lee, I-Ching Tsai, Tai-Wei Kung, Li-Yi Lin, En-Cheng Liu, Yun-Chih Chang, Yih-Lang Li, Mango C.-T. Chao
2022	—	`conf`	Challenges and Approaches in VLSI Routing. ISPD Gracieli Posser, Evangeline F. Y. Young, Stephan Held, Yih-Lang Li, David Z. Pan
2022	J	`jnl`	NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, Hidetoshi Onodera
2022	—	`conf`	Path-Based Pre-Routing Timing Prediction for Modern Very Large-Scale Integration Designs. ISQED Li-Wei Chen, Yao-Nien Sui, Tai-Cheng Lee, Yih-Lang Li, Mango C.-T. Chao, I-Ching Tsai, Tai-Wei Kung, En-Cheng Liu, Yun-Chih Chang
2022	J	`jnl`	Spatiotemporal Activity Semantics Understanding Based on Foreground Object Segmentation: iCounter Scenario. IEEE Access Tzu-Wei Yu, Muhammad Atif Sarwar, Yousef-Awwad Daraghmi, Sheng-Hsien Cheng, Tsì-Uí Ik, Yih-Lang Li
2021	A*	`conf`	A Complete PCB Routing Methodology with Concurrent Hierarchical Routing. DAC Shih-Ting Lin, Hung-Hsiao Wang, Chia-Yu Kuo, Yolo Chen, Yih-Lang Li
2021	A	`conf`	DATC RDF-2021: Design Flow and Beyond ICCAD Special Session Paper. ICCAD Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Seungwon Kim, Victor N. Kravets, Yih-Lang Li, Ravi Varadarajan, Mingyu Woo
2021	J	`jnl`	Supplemental PDK for ASAP7 Using Synopsys Flow. IPSJ Trans. Syst. LSI Des. Methodol. Shinichi Nishizawa, Shih-Ting Lin, Yih-Lang Li, Hidetoshi Onodera
2020	A	`conf`	/TPlace: Machine Learning-Based Delay-Aware Transistor Placement for Standard Cell Synthesis. ICCAD Tai-Cheng Lee, Cheng-Yen Yang, Yih-Lang Li
2020	A	`conf`	DATC RDF-2020: Strengthening the Foundation for Academic Research in IC Physical Design. ICCAD Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Victor N. Kravets, Yih-Lang Li, Shih-Ting Lin, Mingyu Woo
2020	A	`conf`	MCell: Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing. ICCAD Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hidetoshi Onodera
2020	C	`conf`	Smart Self-Checkout Carts Based on Deep Learning for Shopping Activity Recognition. APNOMS Hong-Chuan Chi, Muhammad Atif Sarwar, Yousef-Awwad Daraghmi, Kuan-Wen Liu, Tsì-Uí Ik, Yih-Lang Li
2020	B	`conf`	Smart Shopping Carts Based on Mobile Computing and Deep Learning Cloud Services. WCNC Muhammad Atif Sarwar, Yousef-Awwad Daraghmi, Kuan-Wen Liu, Hong-Chuan Chi, Tsì-Uí Ik, Yih-Lang Li
2019	A	`conf`	DATC RDF-2019: Towards a Complete Academic Reference Design Flow. ICCAD Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Victor N. Kravets, Yih-Lang Li, Shih-Ting Lin, Mingyu Woo
2019	J	`jnl`	Incremental Timing-Driven Placement With Approximated Signoff Wire Delay and Regression-Based Cell Delay. IEEE Trans. Very Large Scale Integr. Syst. Tai-Cheng Lee, Yih-Lang Li
2019	A*	`conf`	NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map. DAC Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, Hidetoshi Onodera
2018	J	`jnl`	A Maze Routing-Based Methodology With Bounded Exploration and Path-Assessed Retracing for Constrained Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction. ACM Trans. Design Autom. Electr. Syst. Kuen-Wey Lin, Yeh-Sheng Lin, Yih-Lang Li, Rung-Bin Lin
2018	J	`jnl`	DATC RDF: An Open Design Flow from Logic Synthesis to Detailed Routing. CoRR Jinwook Jung, Iris Hui-Ru Jiang, Jianli Chen, Shih-Ting Lin, Yih-Lang Li, Victor N. Kravets, Gi-Joon Nam
2018	A	`conf`	DATC RDF: an academic flow from logic synthesis to detailed routing. ICCAD Jinwook Jung, Iris Hui-Ru Jiang, Jianli Chen, Shih-Ting Lin, Yih-Lang Li, Victor N. Kravets, Gi-Joon Nam
2018	J	`jnl`	Fast and Accurate Emissivity and Absolute Temperature Maps Measurement for Integrated Circuits. IEEE Trans. Very Large Scale Integr. Syst. Hsueh-Ling Yu, Yih-Lang Li, Tzu-Yi Liao, Tianchen Wang, Shu-Fei Tsai, Yiyu Shi
2018	A	`conf`	LESAR: A dynamic line-end spacing aware detailed router. DATE Ying-Chi Wei, Radhamanjari Samanta, Yih-Lang Li
2018	—	`conf`	MapReduce-based pattern classification for design space analysis. VLSI-DAT Yan-Shiun Wu, Hong-Yan Su, Yi-Hsiang Chang, Rasit Onur Topaloglu, Yih-Lang Li
2018	—	`conf`	Near-future traffic evaluation based navigation for automated driving vehicles considering traffic uncertainties. ISQED Kuen-Wey Lin, Masanori Hashimoto, Yih-Lang Li
2017	—	`conf`	A Maze Routing-Based Algorithm for ML-OARST with Pre-Selecting and Re-Building Steiner Points. ACM Great Lakes Symposium on VLSI Kuen-Wey Lin, Yeh-Sheng Lin, Yih-Lang Li, Rung-Bin Lin
2017	A	`conf`	DATC RDF: Robust design flow database: Invited paper. ICCAD Jinwook Jung, Pei-Yu Lee, Yan-Shiun Wu, Nima Karimpour Darav, Iris Hui-Ru Jiang, Victor N. Kravets, Laleh Behjat, Yih-Lang Li, Gi-Joon Nam
2017	B	`conf`	Near-future traffic evaluation based navigation for automated driving vehicles. Intelligent Vehicles Symposium Kuen-Wey Lin, Yih-Lang Li, Masanori Hashimoto
2017	—	`conf`	Pin accessibility evaluating model for improving routability of VLSI designs. SoCC Hong-Yan Su, Shinichi Nishizawa, Yan-Shiun Wu, Jun Shiomi, Yih-Lang Li, Hidetoshi Onodera
2016	—	`conf`	Multiple-patterning lithography-aware routing for standard cell layout synthesis. APCCAS Kuen-Wey Lin, Yih-Lang Li, Rung-Bin Lin
2016	A	`conf`	OpenDesign flow database: the infrastructure for VLSI design and design automation research. ICCAD Jinwook Jung, Iris Hui-Ru Jiang, Gi-Joon Nam, Victor N. Kravets, Laleh Behjat, Yih-Lang Li
2015	J	`jnl`	A Novel Fast Layout Encoding Method for Exact Multilayer Pattern Matching With Prüfer Encoding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hong-Yan Su, Chieh-Chu Chen, Yih-Lang Li, An-Chun Tu, Chuh-Jen Wu, Chen-Ming Huang
2015	A	`conf`	SubHunter: a high-performance and scalable sub-circuit recognition method with Prüfer-encoding. DATE Hong-Yan Su, Chih-Hao Hsu, Yih-Lang Li
2014	A*	`conf`	Density-aware Detailed Placement with Instant Legalization. DAC Sergiy Popovych, Hung-Hao Lai, Chieh-Min Wang, Yih-Lang Li, Wen-Hao Liu, Ting-Chi Wang
2014	A	`conf`	Fast and accurate emissivity and absolute temperature maps measurement for integrated circuits. ICCAD Hsueh-Ling Yu, Yih-Lang Li, Tzu-Yi Liao, Tianchen Wang, Yiyu Shi, Shu-Fei Tsai
2014	J	`jnl`	Minimizing Critical Area on Gridless Wire Ordering, Sizing and Spacing. J. Inf. Sci. Eng. Yu-Wei Lee, Yen-Hung Lin, Yih-Lang Li
2014	J	`jnl`	Optimizing the Antenna Area and Separators in Layer Assignment of Multilayer Global Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wen-Hao Liu, Yih-Lang Li
2014	—	`conf`	Skillfully diminishing antenna effect in layer assignment stage. VLSI-DAT Chih-Chien Lin, Wen-Hao Liu, Yih-Lang Li
2014	J	`jnl`	TRIAD: a triple patterning lithography aware detailed router. CoRR Yen-Hung Lin, Bei Yu, David Z. Pan, Yih-Lang Li
2013	—	`conf`	Case study for placement solutions in ispd11 and dac12 routability-driven placement contests. ISPD Wen-Hao Liu, Cheng-Kok Koh, Yih-Lang Li
2013	J	`jnl`	NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, Kai-Yuan Chao
2013	A*	`conf`	Optimization of placement solutions for routability. DAC Wen-Hao Liu, Cheng-Kok Koh, Yih-Lang Li
2013	A*	`conf`	Routing congestion estimation with real design constraints. DAC Wen-Hao Liu, Yaoguang Wei, Cliff C. N. Sze, Charles J. Alpert, Zhuo Li, Yih-Lang Li, Natarajan Viswanathan
2012	A	`conf`	A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing. ICCAD Wen-Hao Liu, Yih-Lang Li, Cheng-Kok Koh
2012	J	`jnl`	NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing. IEEE Trans. Very Large Scale Integr. Syst. Ke-Ren Dai, Wen-Hao Liu, Yih-Lang Li
2012	A	`conf`	Opening: Introduction to CAD contest at ICCAD 2012: CAD contest. ICCAD Iris Hui-Ru Jiang, Zhuo Li, Yih-Lang Li
2012	—	`conf`	Optimizing the antenna area and separators in layer assignment of multi-layer global routing. ISPD Wen-Hao Liu, Yih-Lang Li
2012	A	`conf`	TRIAD: A triple patterning lithography aware detailed router. ICCAD Yen-Hung Lin, Bei Yu, David Z. Pan, Yih-Lang Li
2012	—	`conf`	Topology-aware buffer insertion and GPU-based massively parallel rerouting for ECO timing optimization. ASP-DAC Yen-Hung Lin, Yun-Jian Lo, Hian-Syun Tong, Wen-Hao Liu, Yih-Lang Li
2011	J	`jnl`	A gridless routing system with nonslicing floorplanning-based crosstalk reduction on gridless track assignment. ACM Trans. Design Autom. Electr. Syst. Yih-Lang Li, Yu-Ning Chang, Wen-Nai Cheng
2011	J	`jnl`	Critical-Trunk-Based Obstacle-Avoiding Rectilinear Steiner Tree Routings and Buffer Insertion for Delay and Slack Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yen-Hung Lin, Shu-Hsin Chang, Yih-Lang Li
2011	A	`conf`	Doppler: DPL-aware and OPC-friendly gridless detailed routing with mask density balancing. ICCAD Yen-Hung Lin, Yongchan Ban, David Z. Pan, Yih-Lang Li
2011	—	`conf`	Gridless wire ordering, sizing and spacing with critical area minimization. ISQED Yu-Wei Lee, Yen-Hung Lin, Yih-Lang Li
2011	A	`conf`	High-quality global routing for multiple dynamic supply voltage designs. ICCAD Wen-Hao Liu, Yih-Lang Li, Kai-Yuan Chao
2011	—	`conf`	Negotiation-based layer assignment for via count and via overflow minimization. ASP-DAC Wen-Hao Liu, Yih-Lang Li
2010	—	`conf`	Dead via minimization by simultaneous routing and redundant via insertion. ASP-DAC Chih-Ta Lin, Yen-Hung Lin, Guan-Chan Su, Yih-Lang Li
2010	A*	`conf`	Double patterning lithography aware gridless detailed routing with innovative conflict graph. DAC Yen-Hung Lin, Yih-Lang Li
2010	—	`conf`	Minimizing clock latency range in robust clock tree synthesis. ASP-DAC Wen-Hao Liu, Yih-Lang Li, Hui-Chi Chen
2010	A*	`conf`	Multi-threaded collision-aware global routing with bounded-length maze routing. DAC Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, Kai-Yuan Chao
2009	—	`conf`	Critical-trunk based obstacle-avoiding rectilinear steiner tree routings for delay and slack optimization. ISPD Yen-Hung Lin, Shu-Hsin Chang, Yih-Lang Li
2009	—	`conf`	Efficient simulated evolution based rerouting and congestion-relaxed layer assignment on 3-D global routing. ASP-DAC Ke-Ren Dai, Wen-Hao Liu, Yih-Lang Li
2009	A	`conf`	GRPlacer: Improving routability and wire-length of global routing with circuit replacement. ICCAD Ke-Ren Dai, Chien-Hung Lu, Yih-Lang Li
2009	J	`jnl`	Minimum Shield Insertion on Full-Chip RLC Crosstalk Budgeting Routing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Peng-Yang Hung, Ying-Shu Lou, Yih-Lang Li
2009	C	`conf`	Topology-driven cell layout migration with collinear constraints. ICCD De-Shiun Fu, Ying-Zhih Chaung, Yen-Hung Lin, Yih-Lang Li
2008	J	`jnl`	Design optimization of a current mirror amplifier integrated circuit using a computational statistics technique. Math. Comput. Simul. Yiming Li, Yih-Lang Li, Shao-Ming Yu
2008	J	`jnl`	Electronic design automation using a unified optimization framework. Math. Comput. Simul. Yiming Li, Shao-Ming Yu, Yih-Lang Li
2008	—	`conf`	Minimum Shield Insertion on Full-Chip RLC Crosstalk Budgeting Routing. ISQED Peng-Yang Hung, Ying-Shu Lou, Yih-Lang Li
2008	—	`conf`	Non-slicing floorplanning-based crosstalk reduction on gridless track assignment for a gridless routing system with fast pseudo-tile extraction. ISPD Yu-Ning Chang, Yih-Lang Li, Wei-Tin Lin, Wen-Nai Cheng
2008	J	`jnl`	Parallel solution of large-scale eigenvalue problem for master equation in protein folding dynamics. J. Parallel Distributed Comput. Yiming Li, Shao-Ming Yu, Yih-Lang Li
2007	Misc	`conf`	A Simulation-Based Hybrid Optimization Technique for Low Noise Amplifier Design Automation. International Conference on Computational Science (4) Yiming Li, Shao-Ming Yu, Yih-Lang Li
2007	J	`jnl`	An Efficient Tile-Based ECO Router Using Routing Graph Reduction and Enhanced Global Routing Flow. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yih-Lang Li, Jin-Yih Li, Wen-Bin Chen
2007	J	`jnl`	NEMO: A New Implicit-Connection-Graph-Based Gridless Router With Multilayer Planes and Pseudo Tile Propagation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yih-Lang Li, Hsin-Yu Chen, Chih-Ta Lin
2005	—	`conf`	An efficient tile-based ECO router with routing graph reduction and enhanced global routing flow. ISPD Jin-Yih Li, Yih-Lang Li
1995	J	`jnl`	Cellular automata for efficient parallel logic and fault simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yih-Lang Li, Cheng-Wen Wu
1994	—	`conf`	Logic and Fault Simulation by Cellular Automata. EDAC-ETC-EUROASIC Yih-Lang Li, Cheng-Wen Wu