Yici Cai - RankMe

253 papers A* 8A 17B 3C 24Misc 2Journal 82Unranked 117

Year	Rank	Type	Title / Venue / Authors
2023	J	`jnl`	McPAT-Calib: A RISC-V BOOM Microarchitecture Power Modeling Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou, Bei Yu
2023	J	`jnl`	Microarchitecture Design Space Exploration via Pareto-Driven Active Learning. IEEE Trans. Very Large Scale Integr. Syst. Jianwang Zhai, Yici Cai
2023	—	`conf`	Microarchitecture Power Modeling via Artificial Neural Network and Transfer Learning. ASP-DAC Jianwang Zhai, Yici Cai, Bei Yu
2023	—	`conf`	Static Probability Analysis Guided RTL Hardware Trojan Test Generation. ASP-DAC Haoyi Wang, Qiang Zhou, Yici Cai
2022	J	`jnl`	A survey on machine learning-based routing for VLSI physical design. Integr. Lin Li, Yici Cai, Qiang Zhou
2022	J	`jnl`	Intelligent and kernelized placement: A survey. Integr. Rui Hao, Yici Cai, Qiang Zhou
2022	B	`conf`	TransMarker: A Pure Vision Transformer for Facial Landmark Detection. ICPR Wenyan Wu, Yici Cai, Qiang Zhou
2021	C	`conf`	A Power Grids Electromigration Analysis with Via Array Using Current-Tracing Model. ISCAS Jing Wang, Yici Cai, Qiang Zhou
2021	J	`jnl`	A game theory approach for RTL security verification resources allocation. CCF Trans. High Perform. Comput. Haoyi Wang, Yici Cai, Qiang Zhou
2021	C	`conf`	An Efficient Approach for DRC Hotspot Prediction with Convolutional Neural Network. ISCAS Lin Li, Yici Cai, Qiang Zhou
2021	A	`conf`	McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUs. ICCAD Jianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou, Bei Yu
2021	J	`jnl`	Placement and Routing Methods Considering Shape Constraints of JTL for RSFQ Circuits. IEEE Trans. Circuits Syst. II Express Briefs Jianwang Zhai, Yici Cai, Qiang Zhou
2021	B	`conf`	SRL: Separation-and-Recombination Learning for Video Facial Landmark Detection with Limited Data. FG Wenyan Wu, Yici Cai, Qiang Zhou
2021	J	`jnl`	Temperature-Aware Electromigration Analysis with Current-Tracking in Power Grid Networks. J. Comput. Sci. Technol. Jing Wang, Yici Cai, Qiang Zhou
2020	J	`jnl`	Integrated Control-Fluidic Codesign Methodology for Paper-Based Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Qin Wang, Ulf Schlichtmann, Yici Cai, Weiqing Ji, Zeyan Li, Haena Cheong, Oh-Sun Kwon, Hailong Yao, Tsung-Yi Ho, Kwanwoo Shin, Bing Li
2019	J	`jnl`	A high-level information flow tracking method for detecting information leakage. Integr. Haoyi Wang, Chenguang Wang, Yici Cai, Qiang Zhou
2019	C	`conf`	Composite Optimization for Electromigration Reliability and Noise in Power Grid Networks. ISCAS Jing Wang, Yici Cai, Ming Yan, Qiang Zhou
2019	J	`jnl`	Deep coupling neural network for robust facial landmark detection. Comput. Graph. Wenyan Wu, Xingzhe Wu, Yici Cai, Qiang Zhou
2019	J	`jnl`	Parallelizing SAT-based de-camouflaging attacks by circuit partitioning and conflict avoiding. Integr. Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu
2019	J	`jnl`	Toward a Formal and Quantitative Evaluation Framework for Circuit Obfuscation Methods. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu
2018	J	`jnl`	A Multicommodity Flow-Based Detailed Router With Efficient Acceleration Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiaotao Jia, Yici Cai, Qiang Zhou, Bei Yu
2018	—	`conf`	A conflict-free approach for parallelizing SAT-based de-camouflaging attacks. ASP-DAC Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu
2018	J	`jnl`	AARF: Any-Angle Routing for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kailin Yang, Hailong Yao, Tsung-Yi Ho, Kunze Xin, Yici Cai
2018	—	`conf`	ASAX: Automatic security assertion extraction for detecting Hardware Trojans. ASP-DAC Chenguang Wang, Yici Cai, Qiang Zhou, Haoyi Wang
2018	A	`conf`	Electromagnetic equalizer: an active countermeasure against EM side-channel attack. ICCAD Chenguang Wang, Yici Cai, Haoyi Wang, Qiang Zhou
2018	—	`conf`	Electromigration Design Rule aware Global and Detailed Routing Algorithm. ACM Great Lakes Symposium on VLSI Xiaotao Jia, Jing Wang, Yici Cai, Qiang Zhou
2018	—	`conf`	HLIFT: A high-level information flow tracking method for detecting hardware Trojans. ASP-DAC Chenguang Wang, Yici Cai, Qiang Zhou
2018	A*	`conf`	Look at Boundary: A Boundary-Aware Face Alignment Algorithm. CVPR Wayne Wu, Chen Qian, Shuo Yang, Quan Wang, Yici Cai, Qiang Zhou
2018	J	`jnl`	Look at Boundary: A Boundary-Aware Face Alignment Algorithm. CoRR Wayne Wu, Chen Qian, Shuo Yang, Quan Wang, Yici Cai, Qiang Zhou
2018	J	`jnl`	Physical Co-Design of Flow and Control Layers for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Qin Wang, Hao Zou, Hailong Yao, Tsung-Yi Ho, Robert Wille, Yici Cai
2018	Misc	`conf`	Poet-based Poetry Generation: Controlling Personal Style with Recurrent Neural Networks. ICNC Jia Wei, Qiang Zhou, Yici Cai
2018	J	`jnl`	Spear and Shield: Evolution of Integrated Circuit Camouflaging. J. Comput. Sci. Technol. Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu
2017	—	`conf`	An Effective Power Grid Optimization Approach for the Electromigration Reliability. ISVLSI Ming Yan, Yici Cai, Chenguang Wang, Qiang Zhou
2017	—	`conf`	An Empirical Study on Gate Camouflaging Methods Against Circuit Partition Attack. ACM Great Lakes Symposium on VLSI Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu
2017	C	`conf`	Automatic Security Property Generation for Detecting Information-Leaking Hardware Trojans. ICCD Chenguang Wang, Yici Cai, Qiang Zhou
2017	C	`conf`	Cell spreading optimization for force-directed global placers. ISCAS Xueyan Wang, Yici Cai, Qiang Zhou
2017	—	`conf`	Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips. ASP-DAC Qin Wang, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann, Yici Cai
2017	—	`conf`	LUTOSAP: Lookup Table Based Online Sample Preparation in Microfluidic Biochips. ACM Great Lakes Symposium on VLSI Lingxuan Shao, Yibin Yang, Hailong Yao, Tsung-Yi Ho, Yici Cai
2017	A	`conf`	Physics-based electromigration modeling and assessment for multi-segment interconnects in power grid networks. DATE Xiaoyi Wang, Hongyu Wang, Jian He, Sheldon X.-D. Tan, Yici Cai, Shengqi Yang
2017	C	`conf`	Power Profile Equalizer: A Lightweight Countermeasure against Side-Channel Attack. ICCD Chenguang Wang, Ming Yan, Yici Cai, Qiang Zhou, Jianlei Yang
2017	J	`jnl`	Pressure-Aware Control Layer Optimization for Flow-Based Microfluidic Biochips. IEEE Trans. Biomed. Circuits Syst. Qin Wang, Yue Xu, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann, Yici Cai
2017	—	`conf`	TeenRead: An Adolescents Reading Recommendation System Towards Online Bibliotherapy. BigData Congress Yunxing Xin, Yongqiang Chen, Li Jin, Yici Cai, Ling Feng
2016	C	`conf`	An efficient framework for configurable RO PUF. ISCAS Zhuwei Chen, Yici Cai, Qiang Zhou, Gang Qu
2016	A	`conf`	Control-fluidic CoDesign for paper-based digital microfluidic biochips. ICCAD Qin Wang, Zeyan Li, Haena Cheong, Oh-Sun Kwon, Hailong Yao, Tsung-Yi Ho, Kwanwoo Shin, Bing Li, Ulf Schlichtmann, Yici Cai
2016	J	`jnl`	Integrated Functional and Washing Routing Optimization for Cross-Contamination Removal in Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hailong Yao, Qin Wang, Yiren Shen, Tsung-Yi Ho, Yici Cai
2016	C	`conf`	Is the Secure IC camouflaging really secure? ISCAS Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu
2016	—	`conf`	MCFRoute 2.0: A Redundant Via Insertion Enhanced Concurrent Detailed Router. ACM Great Lakes Symposium on VLSI Xiaotao Jia, Yici Cai, Qiang Zhou, Bei Yu
2016	—	`conf`	Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers. ACM Great Lakes Symposium on VLSI Xueyan Wang, Xiaotao Jia, Qiang Zhou, Yici Cai, Jianlei Yang, Mingze Gao, Gang Qu
2016	—	`conf`	Sequence-pair-based placement and routing for flow-based microfluidic biochips. ASP-DAC Qin Wang, Yizhong Ru, Hailong Yao, Tsung-Yi Ho, Yici Cai
2015	J	`jnl`	A Selected Inversion Approach for Locality Driven Vectorless Power Grid Verification. IEEE Trans. Very Large Scale Integr. Syst. Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao
2015	J	`jnl`	Design-Rule-Aware Congestion Model with Explicit Modeling of Vias and Local Pin Access Paths. J. Comput. Sci. Technol. Zhongdong Qi, Yici Cai, Qiang Zhou
2015	—	`conf`	Early stage real-time SoC power estimation using RTL instrumentation. ASP-DAC Jianlei Yang, Liwei Ma, Kang Zhao, Yici Cai, Tin-Fook Ngai
2015	—	`conf`	Fast synthesis of low power clock trees based on register clustering. ISQED Chao Deng, Yici Cai, Qiang Zhou
2015	J	`jnl`	Integrated Flow-Control Codesign Methodology for Flow-Based Microfluidic Biochips. IEEE Des. Test Hailong Yao, Qin Wang, Yizhong Ru, Yici Cai, Tsung-Yi Ho
2015	J	`jnl`	Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion. IEEE Trans. Very Large Scale Integr. Syst. Yici Cai, Chao Deng, Qiang Zhou, Hailong Yao, Feifei Niu, Cliff N. Sze
2015	A*	`conf`	PACOR: practical control-layer routing flow with length-matching constraint for flow-based microfluidic biochips. DAC Hailong Yao, Tsung-Yi Ho, Yici Cai
2015	J	`jnl`	Register Clustering Methodology for Low Power Clock Tree Synthesis. J. Comput. Sci. Technol. Chao Deng, Yici Cai, Qiang Zhou
2015	J	`jnl`	SIAR: Customized real-time interactive router for analog circuits. Integr. Hailong Yao, Fan Yang, Yici Cai, Qiang Zhou, Chiu-Wing Sham
2015	—	`conf`	SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained EWOD Chips. ISPD Qin Wang, Weiran He, Hailong Yao, Tsung-Yi Ho, Yici Cai
2014	C	`conf`	A register clustering algorithm for low power clock tree synthesis. ISCAS Chao Deng, Yici Cai, Qiang Zhou
2014	C	`conf`	Accurate prediction of detailed routing congestion using supervised data learning. ICCD Zhongdong Qi, Yici Cai, Qiang Zhou
2014	J	`jnl`	Fast and scalable parallel layout decomposition in double patterning lithography. Integr. Wei Zhao, Hailong Yao, Yici Cai, Subarna Sinha, Charles C. Chiang
2014	—	`conf`	Fast vectorless power grid verification using maximum voltage drop location estimation. ASP-DAC Wei Zhao, Yici Cai, Jianlei Yang
2014	J	`jnl`	Friendly Fast Poisson Solver Preconditioning Technique for Power Grid Analysis. IEEE Trans. Very Large Scale Integr. Syst. Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi
2014	J	`jnl`	Length matching in detailed routing for analog and mixed signal circuits. Microelectron. J. Hailong Yao, Qiang Gao, Yici Cai, Qiang Zhou, Chiu-Wing Sham
2014	A	`conf`	MCFRoute: a detailed router based on multi-commodity flow method. ICCAD Xiaotao Jia, Yici Cai, Qiang Zhou, Gang Chen, Zhuoyuan Li, Zuowei Li
2014	—	`conf`	Power supply noise aware evaluation framework for side channel attacks and countermeasures. FPT Jianlei Yang, Chenguang Wang, Yici Cai, Qiang Zhou
2014	J	`jnl`	PowerRush: An Efficient Simulator for Static Power Grid Analysis. IEEE Trans. Very Large Scale Integr. Syst. Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou
2014	A*	`conf`	Practical Functional and Washing Droplet Routing for Cross-Contamination Avoidance in Digital Microfluidic Biochips. DAC Qin Wang, Yiren Shen, Hailong Yao, Tsung-Yi Ho, Yici Cai
2014	—	`conf`	RSMT construction algorithm based on Congestion-Oriented Flexibility. LASCAS Ziyang Qi, Kun Ma, Qiang Zhou, Yici Cai
2014	—	`conf`	Time-domain performance bound analysis for analog and interconnect circuits considering process variations. ASP-DAC Tan Yu, Sheldon X.-D. Tan, Yici Cai, Puying Tang
2014	J	`jnl`	Trusted Integrated Circuits: The Problem and Challenges. J. Comput. Sci. Technol. Yong-Qiang Lv, Qiang Zhou, Yici Cai, Gang Qu
2014	—	`conf`	VFGR: A very fast parallel global router with accurate congestion modeling. ASP-DAC Zhongdong Qi, Yici Cai, Qiang Zhou, Zhuoyuan Li, Mike Chen
2013	—	`conf`	A multilevel ℌ-matrix-based approximate matrix inversion algorithm for vectorless power grid verification. ASP-DAC Wei Zhao, Yici Cai, Jianlei Yang
2013	—	`conf`	A new splitting graph construction algorithm for SIAR router. ASICON Jinming Zhao, Hailong Yao, Yici Cai, Qiang Zhou
2013	—	`conf`	Analog routing considering min-area constraint. ASICON Weijie Chen, Hailong Yao, Yici Cai, Qiang Zhou
2013	—	`conf`	Bridging the Gap between Global Routing and Detailed Routing: A Practical Congestion Model. CAD/Graphics Zhongdong Qi, Yici Cai, Qiang Zhou
2013	—	`conf`	Design and Implementation of a Delay-Based PUF for FPGA IP Protection. CAD/Graphics Jiliang Zhang, Qiang Wu, Yongqiang Lyu, Qiang Zhou, Yici Cai, Yaping Lin, Gang Qu
2013	—	`conf`	Performance bound and yield analysis for analog circuits under process variations. ASP-DAC Xuexin Liu, Adolfo Adair Palma-Rodriguez, Santiago Rodriguez-Chavez, Sheldon X.-D. Tan, Esteban Tlelo-Cuautle, Yici Cai
2013	—	`conf`	SUALD: Spacing uniformity-aware layout decomposition in triple patterning lithography. ISQED Zihao Chen, Hailong Yao, Yici Cai
2013	C	`conf`	Selected inversion for vectorless power grid verification by exploiting locality. ICCD Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao
2013	J	`jnl`	Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs. Integr. Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yuan Xie, Tingting Huang
2012	—	`conf`	A DyadicCluster method used for nonlinear placement. ISQED Wenchao Gao, Qiang Zhou, Xu Qian, Yici Cai
2012	—	`conf`	LEMAR: A novel length matching routing algorithm for analog and mixed signal circuits. ASP-DAC Hailong Yao, Yici Cai, Qiang Gao
2012	A	`conf`	PowerRush : Efficient transient simulation for power grid analysis. ICCAD Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou
2012	—	`conf`	Thermal-aware power network design for IR drop reduction in 3D ICs. ASP-DAC Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yu Wang, Tingting Huang, Yuan Xie
2011	C	`conf`	A fast recursive detailed routing algorithm for hierarchical FPGAs. CSCWD Limin Zhu, Jinian Bian, Qiang Zhou, Yici Cai
2011	—	`conf`	A novel detailed routing algorithm with exact matching constraint for analog and mixed signal circuits. ISQED Qiang Gao, Hailong Yao, Qiang Zhou, Yici Cai
2011	—	`conf`	A novel fine-grain track routing approach for routability and crosstalk optimization. ISQED Zhongdong Qi, Qiang Zhou, Yanming Jia, Yici Cai, Zhuoyuan Li, Hailong Yao
2011	A	`conf`	Fast poisson solver preconditioned method for robust power grid analysis. ICCAD Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi
2011	J	`jnl`	Floorplanning Considering IR Drop in Multiple Supply Voltages Island Designs. IEEE Trans. Very Large Scale Integr. Syst. Qiang Zhou, Jin Shi, Bin Liu, Yici Cai
2011	—	`conf`	Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment. ISVLSI Shuzhe Zhou, Hailong Yao, Qiang Zhou, Yici Cai
2011	—	`conf`	Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization. ACM Great Lakes Symposium on VLSI Feifei Niu, Qiang Zhou, Hailong Yao, Yici Cai, Jianlei Yang, Chin Ngai Sze
2011	A	`conf`	PowerRush: A linear simulator for power grid. ICCAD Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou
2011	—	`conf`	SIAR: splitting-graph-based interactive analog router. ACM Great Lakes Symposium on VLSI Fan Yang, Hailong Yao, Qiang Zhou, Yici Cai
2011	—	`conf`	Statistical full-chip dynamic power estimation considering spatial correlations. ISQED Zhigang Hao, Ruijing Shen, Sheldon X.-D. Tan, Bao Liu, Guoyong Shi, Yici Cai
2010	J	`jnl`	An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement. IEEE Trans. Very Large Scale Integr. Syst. Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
2010	C	`conf`	An architecture-aware routing optimization via satisfiabilty for hierarchical FPGA. CSCWD Limin Zhu, Qiang Zhou, Yici Cai, Jinian Bian
2010	A	`conf`	Analog circuit shielding routing algorithm based on net classification. ISLPED Qiang Gao, Yin Shen, Yici Cai, Hailong Yao
2010	J	`jnl`	ECP- and CMP-Aware Detailed Routing Algorithm for DFM. IEEE Trans. Very Large Scale Integr. Syst. Yin Shen, Qiang Zhou, Yici Cai, Xianlong Hong
2010	—	`conf`	Efficient model reduction of interconnects via double gramians approximation. ASP-DAC Boyuan Yan, Sheldon X.-D. Tan, Gengsheng Chen, Yici Cai
2010	—	`conf`	Efficient power grid integrity analysis using on-the-fly error check and reduction. ASP-DAC Duo Li, Sheldon X.-D. Tan, Ning Mi, Yici Cai
2010	J	`jnl`	Optimization of via distribution and stacked via in multi-layered P/G networks. Integr. Yici Cai, Jin Shi, Shuai Li
2010	A	`conf`	SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal. DATE Fan Yang, Yici Cai, Qiang Zhou, Jiang Hu
2010	—	`conf`	Scaling power/ground solvers on multi-core with memory bandwidth awareness. ACM Great Lakes Symposium on VLSI Jin Shi, Yici Cai
2010	J	`jnl`	Statistical modeling and analysis of chip-level leakage power by spectral stochastic method. Integr. Ruijing Shen, Sheldon X.-D. Tan, Ning Mi, Yici Cai
2010	—	`conf`	Useful clock skew optimization under a multi-corner multi-mode design framework. ISQED Weixiang Shen, Yici Cai, Wei Chen, Yongqiang Lu, Qiang Zhou, Jiang Hu
2010	J	`jnl`	Variational Capacitance Extraction and Modeling Based on Orthogonal Polynomial Method. IEEE Trans. Very Large Scale Integr. Syst. Ruijing Shen, Sheldon X.-D. Tan, Jian Cui, Wenjian Yu, Yici Cai, Gengsheng Chen
2009	J	`jnl`	A single layer zero skew clock routing in X architecture. Sci. China Ser. F Inf. Sci. Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu
2009	—	`conf`	A thermal-driven force-directed floorplanning algorithm for 3D ICs. CAD/Graphics Yun Huang, Qiang Zhou, Yici Cai, Haixia Yan
2009	J	`jnl`	An MTCMOS technology for low-power physical design. Integr. Qiang Zhou, Xin Zhao, Yici Cai, Xianlong Hong
2009	A	`conf`	An efficient decoupling capacitance optimization using piecewise polynomial models. DATE Xiaoyi Wang, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Jacob Relles
2009	—	`conf`	Cell shifting aware of wirelength and overlap. ISQED Dawei Liu, Qiang Zhou, Jinian Bian, Yici Cai, Xianlong Hong
2009	A	`conf`	Decoupling capacitance efficient placement for reducing transient power supply noise. ICCAD Xiaoyi Wang, Yici Cai, Qiang Zhou, Sheldon X.-D. Tan, Thom Jefferson A. Eguia
2009	C	`conf`	Fast congestion-aware timing-driven placement for island FPGA. DDECS Jinpeng Zhao, Qiang Zhou, Yici Cai
2009	—	`conf`	Fast placement for large-scale hierarchical FPGAs. CAD/Graphics Hui Dai, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong
2009	A*	`conf`	GPU friendly fast Poisson solver for structured power grid network analysis. DAC Jin Shi, Yici Cai, Wenting Hou, Liwei Ma, Sheldon X.-D. Tan, Pei-Hsin Ho, Xiaoyi Wang
2009	—	`conf`	Statistical modeling and analysis of chip-level leakage power by spectral stochastic method. ASP-DAC Ruijing Shen, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong
2008	—	`conf`	A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation. ISVLSI Yibo Wang, Yici Cai, Xianlong Hong
2008	—	`conf`	A novel performance driven power gating based on distributed sleep transistor network. ACM Great Lakes Symposium on VLSI Liangpeng Guo, Yici Cai, Qiang Zhou, Le Kang, Xianlong Hong
2008	—	`conf`	Activity and register placement aware gated clock network design. ISPD Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
2008	J	`jnl`	Application of optical proximity correction technology. Sci. China Ser. F Inf. Sci. Yici Cai, Qiang Zhou, Xianlong Hong, Rui Shi, Yang Wang
2008	—	`conf`	DFM Based Detailed Routing Algorithm for ECP and CMP. ISQED Yin Shen, Yici Cai, Qiang Zhou, Xianlong Hong
2008	J	`jnl`	Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yanming Jia, Yici Cai, Xianlong Hong
2008	J	`jnl`	Early Stage Power Supply Planning: A Heuristic Method for Codesign of Power/Ground Network and Floorplan. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong
2008	J	`jnl`	Efficient range pattern matching algorithm for process-hotspot detection. IET Circuits Devices Syst. Hailong Yao, Subarna Sinha, Jingyu Xu, Charles C. Chiang, Yici Cai, Xianlong Hong
2008	J	`jnl`	Fast Variational Analysis of On-Chip Power Grids by Stochastic Extended Krylov Subspace Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong
2008	—	`conf`	Full-chip routing system for reducing Cu CMP & ECP variation. SBCCI Yanming Jia, Yici Cai, Xianlong Hong
2008	C	`conf`	Gate planning during placement for gated clock network. ICCD Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
2008	—	`conf`	Heuristic power/ground network and floorplan co-design method. ASP-DAC Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong
2008	J	`jnl`	Large scale P/G grid transient simulation using hierarchical relaxed approach. Integr. Yici Cai, Jin Shi, Zhu Pan, Xianlong Hong, Sheldon X.-D. Tan
2008	C	`conf`	Leakage power optimization for clock network using dual-Vth technology. ISCAS Weixiang Shen, Yici Cai, Xianlong Hong
2008	J	`jnl`	Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong
2008	J	`jnl`	Low Power Gated Clock Tree Driven Placement. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
2008	—	`conf`	Low power clock buffer planning methodology in F-D placement for large scale circuit design. ASP-DAC Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian
2008	B	`conf`	MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation. FPL Xing Wei, Juanjuan Chen, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong
2008	J	`jnl`	Random Walk Guided Decap Embedding for Power/Ground Network Optimization. IEEE Trans. Circuits Syst. II Express Briefs Yici Cai, Le Kang, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan
2008	J	`jnl`	Statistical Analysis of On-Chip Power Delivery Networks Considering Lognormal Leakage Current Variations With Spatial Correlation. IEEE Trans. Circuits Syst. I Regul. Pap. Ning Mi, Jeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong
2008	—	`conf`	Vertical via design techniques for multi-layered P/G networks. ASP-DAC Shuai Li, Jin Shi, Yici Cai, Xianlong Hong
2008	—	`conf`	Wire density driven top-down global placement for CMP variation control. APCCAS Changdao Dong, Qiang Zhou, Yici Cai, Xianlong Hong
2008	J	`jnl`	Zero skew clock routing in X-architecture based on an improved greedy matching algorithm. Integr. Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu
2007	J	`jnl`	A Yield-Driven Gridless Router. J. Comput. Sci. Technol. Qiang Zhou, Yici Cai, Duo Li, Xianlong Hong
2007	—	`conf`	Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction. ISVLSI Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
2007	J	`jnl`	An efficient quadratic placement based on search space traversing technology. Integr. Yongqiang Lu, Xianlong Hong, Qiang Zhou, Yici Cai, Jun Gu
2007	—	`conf`	CMP-aware Maze Routing Algorithm for Yield Enhancement. ISVLSI Hailong Yao, Yici Cai, Xianlong Hong
2007	C	`conf`	Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building. ISCAS Yanfeng Wang, Qiang Zhou, Xianlong Hong, Yici Cai
2007	—	`conf`	Dummy fill aware buffer insertion during routing. ACM Great Lakes Symposium on VLSI Yanming Jia, Yici Cai, Xianlong Hong
2007	C	`conf`	Effective Acceleration of Iterative Slack Distribution Process. ISCAS Xinjie Wei, Yici Cai, Xianlong Hong
2007	—	`conf`	Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach. ASP-DAC Le Kang, Yici Cai, Yi Zou, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan
2007	—	`conf`	Logic and Layout Aware Voltage Island Generation for Low Power Design. ASP-DAC Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong
2007	—	`conf`	New timing and routability driven placement algorithms for FPGA synthesis. ACM Great Lakes Symposium on VLSI Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong Hong
2007	J	`jnl`	Partitioning-based decoupling capacitor budgeting via sequence of linear programming. Integr. Jeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong
2007	J	`jnl`	Pattern-Based Iterative Method for Extreme Large Power/Ground Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jin Shi, Yici Cai, Sheldon X.-D. Tan, Jeffrey Fan, Xianlong Hong
2007	—	`conf`	Physical aware clock skew rescheduling. ACM Great Lakes Symposium on VLSI Xinjie Wei, Yici Cai, Xianlong Hong
2007	—	`conf`	Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture. ISQED Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu
2007	—	`conf`	Power Delivery Aware Floorplanning for Voltage Island Designs. ISQED Yici Cai, Bin Liu, Jin Shi, Qiang Zhou, Xianlong Hong
2007	—	`conf`	Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos. ASP-DAC Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan, Le Kang
2007	—	`conf`	Simultaneous Switching Noise Consideration for Power/Ground Network Optimization. CAD/Graphics Le Kang, Yici Cai, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan, Xiaoyi Wang
2007	A	`conf`	Statistical model order reduction for interconnect circuits considering spatial correlations. DATE Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong
2007	J	`jnl`	Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yibo Wang, Yici Cai, Xianlong Hong, Yi Zou
2007	A	`conf`	Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks. ICCAD Ning Mi, Sheldon X.-D. Tan, Pu Liu, Jian Cui, Yici Cai, Xianlong Hong
2007	J	`jnl`	Voltage Island Generation in Cell Based Dual-Vdd Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong
2006	J	`jnl`	A Two-Step Heuristic Algorithm for Minimum-Crosstalk Routing Resource Assignment. IEEE Trans. Circuits Syst. II Express Briefs Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong
2006	C	`conf`	A novel low-power physical design methodology for MTCMOS. ISCAS Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong
2006	C	`conf`	A novel technique integrating buffer insertion into timing driven placement. ISCAS Lijuan Luo, Qiang Zhou, Yici Cai, Xianlong Hong, Yibo Wang
2006	—	`conf`	Clock Skew Scheduling Under Process Variations. ISQED Xinjie Wei, Yici Cai, Xianlong Hong
2006	C	`conf`	Congestion-driven W-shape multilevel full-chip routing framework. ISCAS Hailong Yao, Yici Cai, Xianlong Hong
2006	—	`conf`	DFM-aware Routing for Yield Enhancement. APCCAS Xianlong Hong, Yici Cai, Hailong Yao, Duo Li
2006	—	`conf`	Efficient early stage resonance estimation techniques for C4 package. ASP-DAC Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong
2006	A	`conf`	Efficient process-hotspot detection using range pattern matching. ICCAD Hailong Yao, Subarna Sinha, Charles C. Chiang, Xianlong Hong, Yici Cai
2006	J	`jnl`	Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng
2006	—	`conf`	High accurate pattern based precondition method for extremely large power/ground grid analysis. ISPD Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong
2006	C	`conf`	High performance clock routing in X-architecture. ISCAS Weixiang Shen, Yici Cai, Jiang Hu, Xianlong Hong, Bing Lu
2006	J	`jnl`	Legitimate Skew Clock Routing with Buffer Insertion. J. VLSI Signal Process. Xinjie Wei, Yici Cai, Meng Zhao, Xianlong Hong
2006	—	`conf`	Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming. ISQED Jeffrey Fan, I-Fan Liao, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong
2006	J	`jnl`	Multilevel Routing With Redundant Via Insertion. IEEE Trans. Circuits Syst. II Express Briefs Hailong Yao, Yici Cai, Qiang Zhou, Xianlong Hong
2006	J	`jnl`	Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hang Li, Jeffrey Fan, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong
2006	C	`conf`	Performance and power aware buffered tree construction. ISCAS Yibo Wang, Yici Cai, Xianlong Hong
2006	—	`conf`	Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs. ASP-DAC Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong
2006	J	`jnl`	Power/Ground Network Optimization Considering Decap Leakage Currents. IEEE Trans. Circuits Syst. II Express Briefs Yici Cai, Jingjing Fu, Xianlong Hong, Sheldon X.-D. Tan, Zuying Luo
2006	J	`jnl`	Priority-Based Routing Resource Assignment Considering Crosstalk. J. Comput. Sci. Technol. Yici Cai, Bin Liu, Yan Xiong, Qiang Zhou, Xianlong Hong
2006	J	`jnl`	Time-domain analysis methodology for large-scale RLC circuits and its applications. Sci. China Ser. F Inf. Sci. Zuying Luo, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Xiaoyi Wang, Zhu Pan, Jingjing Fu
2006	—	`conf`	Variational Circuit Simulator based on a Unified Methodology using Arithmetic over Taylor Polynomials. APCCAS Qiang Zhou, Yi Zou, Yici Cai, Xianlong Hong
2005	Misc	`conf`	A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model. VLSI Design Yibo Wang, Yici Cai, Xianlong Hong
2005	J	`jnl`	A Fast Delay Computation for the Hybrid Structured Clock Network. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan
2005	—	`conf`	A Hybrid Genetic Algorithm and Application to the Crosstalk Aware Track Assignment Problem. ICNC (3) Yici Cai, Bin Liu, Xiong Yan, Qiang Zhou, Xianlong Hong
2005	—	`conf`	A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design. PATMOS Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong
2005	—	`conf`	A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. ISCAS (6) Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani
2005	—	`conf`	A global interconnect optimization algorithm under accurate delay model using solution space smoothing. ISCAS (1) Yici Cai, Yibo Wang, Xianlong Hong
2005	—	`conf`	A new algorithm for layout of dark field alternating phase shifting masks. ACM Great Lakes Symposium on VLSI Qinglang Luo, Xianlong Hong, Qiang Zhou, Yici Cai
2005	—	`conf`	An efficient algorithm for buffered routing tree construction under fixed buffer locations with accurate delay models. ISCAS (1) Yiqian Zhang, Xianlong Hong, Yici Cai
2005	—	`conf`	Analysis of buffered hybrid structured clock networks. ASP-DAC Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan
2005	—	`conf`	Clock network minimization methodology based on incremental placement. ASP-DAC Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu
2005	J	`jnl`	Crosstalk and Congestion Driven Layer Assignment Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong
2005	J	`jnl`	Crosstalk-Aware Routing Resource Assignment. J. Comput. Sci. Technol. Hailong Yao, Yici Cai, Qiang Zhou, Xianlong Hong
2005	—	`conf`	Efficient Simulation of Power/Ground Networks with Package and Vias. PATMOS Jin Shi, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan
2005	—	`conf`	Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery. ISQED Zhenyu Qi, Hang Li, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong
2005	—	`conf`	Improved multilevel routing with redundant via placement for yield and reliability. ACM Great Lakes Symposium on VLSI Hailong Yao, Yici Cai, Xianlong Hong, Qiang Zhou
2005	—	`conf`	Integrated routing resource assignment for RLC crosstalk minimization. ISCAS (2) Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong
2005	J	`jnl`	Modeling and Analysis of Mesh Tree Hybrid Power/Ground Networks with Multiple Voltage Supply in Time Domain. J. Comput. Sci. Technol. Yici Cai, Jin Shi, Zuying Luo, Xianlong Hong
2005	J	`jnl`	Navigating Register Placement for Low Power Clock Network Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yongqiang Lu, Chin Ngai Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
2005	A*	`conf`	Navigating registers in placement for clock network minimization. DAC Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
2005	A*	`conf`	Partitioning-based approach to fast on-chip decap budgeting and minimization. DAC Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong
2005	—	`conf`	Register placement for low power clock network. ASP-DAC Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
2005	—	`conf`	Relaxed hierarchical power/ground grid analysis. ASP-DAC Yici Cai, Zhu Pan, Sheldon X.-D. Tan, Xianlong Hong, Wenting Hou, Lifeng Wu
2005	J	`jnl`	Reliable buffered clock tree routing algorithm with process variation tolerance. Sci. China Ser. F Inf. Sci. Yici Cai, Yan Xiong, Xianlong Hong, Yi Liu
2005	J	`jnl`	Shielding Area Optimization Under the Solution of Interconnect Crosstalk. J. Comput. Sci. Technol. Yici Cai, Xin Zhao, Qiang Zhou, Xianlong Hong
2005	—	`conf`	VLSI on-chip power/ground network optimization considering decap leakage currents. ASP-DAC Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan
2005	—	`conf`	Zero skew clock routing with tree topology construction using simulated annealing method. ISCAS (1) Xinjie Wei, Yici Cai, Xianlong Hong
2004	C	`conf`	A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network. ICCD Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan
2004	J	`jnl`	A buffer planning algorithm for chip-level floorplanning. Sci. China Ser. F Inf. Sci. Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004	—	`conf`	A buffer planning algorithm with congestion optimization. ASP-DAC Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004	—	`conf`	A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery. ASP-DAC Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan
2004	—	`conf`	Algorithm for yield driven correction of layout. ISCAS (5) Yang Wang, Yici Cai, Xianlong Hong, Qiang Zhou
2004	J	`jnl`	Area minimization of power distribution network using efficient nonlinear programming techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiaohai Wu, Xianlong Hong, Yici Cai, Zuying Luo, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai
2004	—	`conf`	Buffer allocation algorithm with consideration of routing congestion. ASP-DAC Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004	J	`jnl`	Corner block list representation and its application to floorplan optimization. IEEE Trans. Circuits Syst. II Express Briefs Xianlong Hong, Sheqin Dong, Gang Huang, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004	J	`jnl`	Corner block list representation and its application with boundary constraints. Sci. China Ser. F Inf. Sci. Xianlong Hong, Yuchun Ma, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004	—	`conf`	Crosstalk driven routing resource assignment. ISCAS (5) Hailong Yao, Qiang Zhou, Xianlong Hong, Yici Cai
2004	—	`conf`	Layer assignment algorithm for RLC crosstalk minimization. ISCAS (5) Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong
2004	—	`conf`	Quick and effective buffered legitimate skew clock routing. ISCAS (5) Meng Zhao, Xinjie Wei, Yici Cai, Xianlong Hong
2004	—	`conf`	Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration. ISCAS (5) Changqi Yang, Xianlong Hong, Hannah Honghua Yang, Qiang Zhou, Yici Cai, Yongqiang Lu
2004	—	`conf`	Shielding area optimization under the solution of interconnect crosstalk. ISCAS (5) Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong, Lei He, Jinjun Xiong
2004	—	`conf`	Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery. PATMOS Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan
2004	J	`jnl`	Stairway compaction using corner block list and its applications with rectilinear blocks. ACM Trans. Design Autom. Electr. Syst. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004	—	`conf`	Transient Analysis of On-Chip Power Distribution Networks Using Equivalent Circuit Modeling. ISQED Zhu Pan, Yici Cai, Sheldon X.-D. Tan, Zuying Luo, Xianlong Hong
2003	J	`jnl`	A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu
2003	—	`conf`	A buffer planning algorithm based on dead space redistribution. ASP-DAC Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
2003	—	`conf`	A novel timing-driven global routing algorithm considering coupling effects for high performance circuit design. ASP-DAC Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu
2003	—	`conf`	A path-based timing-driven quadratic placement algorithm. ASP-DAC Wenting Hou, Xianlong Hong, Weimin Wu, Yici Cai
2003	J	`jnl`	An efficient hierarchical timing-driven Steiner tree algorithm for global routing. Integr. Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu
2003	—	`conf`	An integrated floorplanning with an efficient buffer planning algorithm. ISPD Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
2003	—	`conf`	Arbitrary convex and concave rectilinear block packing based on corner block list. ISCAS (5) Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu
2003	—	`conf`	Combining clustering and partitioning in quadratic placement. ISCAS (4) Yongqiang Lu, Xianlong Hong, Wenting Hou, Weimin Wu, Yici Cai
2003	A*	`conf`	Dynamic global buffer planning optimization based on detail block locating and congestion analysis. DAC Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
2003	—	`conf`	Evaluating a bounded slice-line grid assignment in O(nlogn) time. ISCAS (4) Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
2003	J	`jnl`	FaSa: A Fast and Stable Quadratic Placement Algorithm. J. Comput. Sci. Technol. Wenting Hou, Xianlong Hong, Weimin Wu, Yici Cai
2003	—	`conf`	UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing. ASP-DAC Tong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Chung-Kuan Cheng, Jun Gu
2002	J	`jnl`	A multi-step standard-cell placement algorithm of optimizing timing and congestion behavior. Sci. China Ser. F Inf. Sci. Wenting Hou, Xianlong Hong, Weimin Wu, Yici Cai
2002	—	`conf`	A novel and efficient timing-driven global router for standard cell layout design based on critical network concept. ISCAS (1) Tong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Jun Gu
2002	—	`conf`	An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing. ASP-DAC/VLSI Design Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu
2002	J	`jnl`	An Optimum Placement Search Algorithm Based on Extended Corner Block List. J. Comput. Sci. Technol. Sheqin Dong, Shuo Zhou, Xianlong Hong, Chung-Kuan Cheng, Jun Gu, Yici Cai
2002	—	`conf`	Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. ASP-DAC/VLSI Design Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2001	—	`conf`	A new congestion-driven placement algorithm based on cell inflation. ASP-DAC Wenting Hou, Hong Yu, Xianlong Hong, Yici Cai, Weimin Wu, Jun Gu, William H. Kao
2001	A	`conf`	Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques. ICCAD Xiaohai Wu, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai
2001	A*	`conf`	Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. DAC Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2001	J	`jnl`	Floorplanning with abutment constraints based on corner block list. Integr. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2001	—	`conf`	VLSI floorplanning with boundary constraints based on corner block list. ASP-DAC Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2000	—	`conf`	Area routing oriented hierarchical corner stitching with partial bin. ASP-DAC Yan Zhang, Baohua Wang, Yici Cai, Xianlong Hong
2000	A	`conf`	Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan. ICCAD Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, Jun Gu
2000	—	`conf`	MMP: a novel placement algorithm for combined macro block and standard cell layout design. ASP-DAC Hong Yu, Xianlong Hong, Yici Cai
1999	—	`conf`	A New Global Routing Algorithm Independent Of Net Ordering. ASP-DAC Haiyun Bao, Xianlong Hong, Yici Cai
1999	—	`conf`	A Timing-Driven Block Placer Based on Sequence Pair Model. ASP-DAC Gang Huang, Xianlong Hong, Changge Qiao, Yici Cai