Yichao Zhang

30 papers A* 1A 3B 1C 1Journal 18Unranked 6
YearRankTypeTitle / Venue / Authors
2026 J jnl
TeraPool: A Physical Design Aware, 1024 RISC-V Cores Shared-L1-Memory Scaled-up Cluster Design with High Bandwidth Main Memory Link.
CoRR
Yichao Zhang, Marco Bertuletti, Chi Zhang, Samuel Riedel, Diyou Shen, Bowen Wang, Alessandro Vanelli-Coralli, Luca Benini
2025 J jnl
A 410GFLOP/s, 64 RISC-V Cores, 204.8GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN.
CoRR
Yichao Zhang, Marco Bertuletti, Sergio Mazzola, Samuel Riedel, Luca Benini
2025 J jnl
A 66-Gb/s/5.5-W RISC-V Many-Core Cluster for 5G+ Software-Defined Radio Uplinks.
IEEE Trans. Very Large Scale Integr. Syst.
Marco Bertuletti, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini
2025 B conf
A Compute&Memory Efficient Model-Driven Neural 5G Receiver for Edge AI-assisted RAN.
GLOBECOM
Mahdi Abdollahpour, Marco Bertuletti, Yichao Zhang, Yawei Li, Luca Benini, Alessandro Vanelli-Coralli
2025 — conf
A Dynamic Allocation Scheme for Adaptive Shared-Memory Mapping on Kilo-Core RV Clusters for Attention-Based Model Deployment.
ASAP
Bowen Wang, Marco Bertuletti, Yichao Zhang, Victor J. B. Jung, Luca Benini
2025 J jnl
A Dynamic Allocation Scheme for Adaptive Shared-Memory Mapping on Kilo-core RV Clusters for Attention-Based Model Deployment.
CoRR
Bowen Wang, Marco Bertuletti, Yichao Zhang, Victor J. B. Jung, Luca Benini
2025 A* conf
Fast End-to-End Simulation and Exploration of Many-RISCV-Core Baseband Transceivers for Software-Defined Radio-Access Networks.
DAC
Marco Bertuletti, Yichao Zhang, Mahdi Abdollahpour, Samuel Riedel, Alessandro Vanelli-Coralli, Luca Benini
2025 J jnl
MemPool Flavors: Between Versatility and Specialization in a RISC-V Manycore Cluster.
CoRR
Sergio Mazzola, Yichao Zhang, Marco Bertuletti, Diyou Shen, Luca Benini
2025 J jnl
Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET.
IEEE J. Solid State Circuits
Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus A. Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025 J jnl
Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET.
CoRR
Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus A. Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025 — conf
Optimizing Scalable Multi-Cluster Architectures for Next-Generation Wireless Sensing and Communication.
IWASI
Samuel Riedel, Yichao Zhang, Marco Bertuletti, Luca Benini
2025 J jnl
Optimizing Scalable Multi-Cluster Architectures for Next-Generation Wireless Sensing and Communication.
CoRR
Samuel Riedel, Yichao Zhang, Marco Bertuletti, Luca Benini
2025 A conf
TCDM Burst Access: Breaking the Bandwidth Barrier in Shared-L1 RVV Clusters Beyond 1000 FPUs.
DATE
Diyou Shen, Yichao Zhang, Marco Bertuletti, Luca Benini
2025 J jnl
TCDM Burst Access: Breaking the Bandwidth Barrier in Shared-L1 RVV Clusters Beyond 1000 FPUs.
CoRR
Diyou Shen, Yichao Zhang, Marco Bertuletti, Luca Benini
2025 C conf
TeraNOC: A Multi-Channel 32-Bit Fine-Grained, Hybrid Mesh-Crossbar Noc for Efficient Scale-Up of 1000+ Core Shared-L1-Memory Clusters.
ICCD
Yichao Zhang, Zexin Fu, Tim Fischer, Yinrong Li, Marco Bertuletti, Luca Benini
2025 J jnl
TeraNoC: A Multi-Channel 32-bit Fine-Grained, Hybrid Mesh-Crossbar NoC for Efficient Scale-up of 1000+ Core Shared-L1-Memory Clusters.
CoRR
Yichao Zhang, Zexin Fu, Tim Fischer, Yinrong Li, Marco Bertuletti, Luca Benini
2025 J jnl
TeraPool: A Physical Design Aware, 1024 RISC-V Cores Shared-L1-Memory Scaled-Up Cluster Design With High Bandwidth Main Memory Link.
IEEE Trans. Computers
Yichao Zhang, Marco Bertuletti, Chi Zhang, Samuel Riedel, Diyou Shen, Bowen Wang, Alessandro Vanelli-Coralli, Luca Benini
2024 J jnl
A 1024 RV-Cores Shared-L1 Cluster with High Bandwidth Memory Link for Low-Latency 6G-SDR.
CoRR
Yichao Zhang, Marco Bertuletti, Chi Zhang, Samuel Riedel, Alessandro Vanelli-Coralli, Luca Benini
2024 A conf
MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication.
DATE
Matteo Perotti, Yichao Zhang, Matheus A. Cavalcante, Enis Mustafa, Luca Benini
2024 J jnl
MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication.
CoRR
Matteo Perotti, Yichao Zhang, Matheus A. Cavalcante, Enis Mustafa, Luca Benini
2024 — conf
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET.
VLSI Technology and Circuits
Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2024 J jnl
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET.
CoRR
Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2024 — conf
TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios.
ACM Great Lakes Symposium on VLSI
Yichao Zhang, Marco Bertuletti, Samuel Riedel, Matheus A. Cavalcante, Alessandro Vanelli-Coralli, Luca Benini
2024 J jnl
TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios.
CoRR
Yichao Zhang, Marco Bertuletti, Samuel Riedel, Matheus A. Cavalcante, Alessandro Vanelli-Coralli, Luca Benini
2023 A conf
Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-Core Processor.
DATE
Marco Bertuletti, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini
2023 — conf
Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster.
SAMOS
Marco Bertuletti, Samuel Riedel, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini
2023 J jnl
Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster.
CoRR
Marco Bertuletti, Samuel Riedel, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini
2022 J jnl
Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-core Processor.
CoRR
Marco Bertuletti, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini
2022 — conf
Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters.
ISVLSI
Gianna Paulin, Matheus A. Cavalcante, Paul Scheffler, Luca Bertaccini, Yichao Zhang, Frank K. Gürkaynak, Luca Benini
2022 J jnl
Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters.
CoRR
Gianna Paulin, Matheus A. Cavalcante, Paul Scheffler, Luca Bertaccini, Yichao Zhang, Frank K. Gürkaynak, Luca Benini