Yibo Lin

246 papers A* 42A 52C 4Journal 105Unranked 42
YearRankTypeTitle / Venue / Authors
2026 J jnl
A Post-Routing Layout Optimization Framework for Lithography Process Window Enlargement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yajuan Su, Zixi Liu, Yibo Lin, Xiaojing Su, Yuqin Wang, Xin Hong, Yujie Jiang, Pengyu Ren, Yayi Wei
2026 — conf
AC-Refiner: Efficient Arithmetic Circuit Optimization Using Conditional Diffusion Models.
ASP-DAC
Chenhao Xue, Kezhi Li, Jiaxing Zhang, Yi Ren, Zhengyuan Shi, Chen Zhang, Yibo Lin, Lining Zhang, Qiang Xu, Guangyu Sun
2026 J jnl
CellE: Automated Standard Cell Library Extension via Equality Saturation.
CoRR
Yi Ren, Yukun Wang, Xiang Meng, Guoyao Cheng, Baokang Peng, Lining Zhang, Yibo Lin, Runsheng Wang, Guangyu Sun
2026 J jnl
G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner using Task Graph Parallelism.
ACM Trans. Design Autom. Electr. Syst.
Wan-Luan Lee, Dian-Lun Lin, Shui Jiang, Cheng-Hsiang Chiu, Yibo Lin, Bei Yu, Tsung-Yi Ho, Tsung-Wei Huang
2026 — conf
HeteroLatch: A CPU-GPU Heterogeneous Latch-Aware Timing Analysis Engine.
ASP-DAC
Xizhe Shi, Zizheng Guo, Yibo Lin, Zuodong Zhang, Yun Liang, Runsheng Wang
2026 — conf
HeteroSTA: A CPU-GPU Heterogeneous Static Timing Analysis Engine with Holistic Industrial Design Support.
ASP-DAC
Zizheng Guo, Haichuan Liu, Xizhe Shi, Shenglu Hua, Zuodong Zhang, Chunyuan Zhao, Runsheng Wang, Yibo Lin
2026 — conf
IR Drop-Aware ECO: A Fast Approach to Minimize Layout and Timing Disturbance.
ASP-DAC
Jingchao Hu, Yibo Lin, Hao Yu, Quan Chen, Zhou Jin, Cheng Zhuo
2026 J jnl
Introduction to the Special Issue on Machine Learning for CAD, Part I.
ACM Trans. Design Autom. Electr. Syst.
Yibo Lin, Siddharth Garg, Hussam Amrouch, Cong Hao
2026 J jnl
LEGALM 2.0: A Versatile Augmented Lagrangian Method-Based Methodology for Mixed-Cell-Height Legalization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jing Mai, Chunyuan Zhao, Zuodong Zhang, Zhixiong Di, Runsheng Wang, Yibo Lin
2026 — conf
MOSTAR: Multi-Stage Hierarchical Bayesian Optimization for Substructure-Aware High-Dimensional Analog Circuit Sizing.
ASP-DAC
Weijian Fan, Haoyi Zhang, Weibin Lin, Runsheng Wang, Yibo Lin
2026 J jnl
RegPlace: Regularity-Aware Placement for Full-System DNN Accelerator Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jiaxi Jiang, Yuan Pu, Mingjun Li, Yuxuan Zhao, Peiyu Liao, Zuodong Zhang, Yibo Lin, Bei Yu
2026 J jnl
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs.
ACM Trans. Design Autom. Electr. Syst.
Siting Liu, Jieya Zhou, Jiaxi Jiang, Zhuolun He, Ziyi Wang, Yibo Lin, Bei Yu, Martin D. F. Wong
2026 — conf
Standard Cell Layout Synthesis for Dual-Sided 3D-Stacked Transistors.
ASP-DAC
Kairong Guo, Haoran Lu, Rui Guo, Jiarui Wang, Chunyuan Zhao, Heng Wu, Runsheng Wang, Yibo Lin
2026 A conf
TDM Signal Grouping and Package Pin Assignment for 2.5D Multi-FPGA Systems with Lookahead Placement.
FPGA
Jiarui Wang, Runzhe Tao, Jing Mai, Xun Jiang, Shenghua Wang, Cuiliu Yang, Haoyu Jie, Kan Huang, Richard Y. Sun, Yibo Lin
2025 J jnl
A Robust FPGA Router With Optimization of High-Fanout Nets and Intra-CLB Connections.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xun Jiang, Jiarui Wang, Jing Mai, Zhixiong Di, Yibo Lin
2025 A* conf
A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis.
DAC
Xun Jiang, Haoran Lu, Yuxuan Zhao, Jiarui Wang, Zizheng Guo, Heng Wu, Bei Yu, Sung Kyu Lim, Runsheng Wang, Ru Huang, Yibo Lin
2025 J jnl
A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis.
CoRR
Xun Jiang, Haoran Lu, Yuxuan Zhao, Jiarui Wang, Zizheng Guo, Heng Wu, Bei Yu, Sung Kyu Lim, Runsheng Wang, Ru Huang, Yibo Lin
2025 A conf
A Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-Sided Signals.
DATE
Haoran Lu, Xun Jiang, Yanbang Chu, Ziqiao Xu, Rui Guo, Wanyue Peng, Yibo Lin, Runsheng Wang, Heng Wu, Ru Huang
2025 J jnl
A Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-sided Signals.
CoRR
Haoran Lu, Xun Jiang, Yanbang Chu, Ziqiao Xu, Rui Guo, Wanyue Peng, Yibo Lin, Runsheng Wang, Heng Wu, Ru Huang
2025 J jnl
A Unified Deep Reinforcement Learning Approach for Constructing Rectilinear and Octilinear Steiner Minimum Tree.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhenkun Lin, Genggeng Liu, Xing Huang, Yibo Lin, Jixin Zhang, Wen-Hao Liu, Ting-Chi Wang
2025 J jnl
AC-Refiner: Efficient Arithmetic Circuit Optimization Using Conditional Diffusion Models.
CoRR
Chenhao Xue, Kezhi Li, Jiaxing Zhang, Yi Ren, Zhengyuan Shi, Chen Zhang, Yibo Lin, Lining Zhang, Qiang Xu, Guangyu Sun
2025 J jnl
ATMPlace: Analytical Thermo-Mechanical-Aware Placement Framework for 2.5D-IC.
CoRR
Qipan Wang, Tianxiang Zhu, Tianyu Jia, Yibo Lin, Runsheng Wang, Ru Huang
2025 J jnl
Analytical Heterogeneous Die-to-Die 3-D Placement With Macros.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuxuan Zhao, Peiyu Liao, Siting Liu, Jiaxi Jiang, Yibo Lin, Bei Yu
2025 J jnl
DOMAC: Differentiable Optimization for High-Speed Multipliers and Multiply-Accumulators.
CoRR
Chenhao Xue, Yi Ren, Jinwei Zhou, Kezhi Li, Chen Zhang, Yibo Lin, Lining Zhang, Qiang Xu, Guangyu Sun
2025 A* conf
DeepLayout: Learning Neural Representations of Circuit Placement Layout.
ICML
Yuxiang Zhao, Zhuomin Chai, Xun Jiang, Qiang Xu, Runsheng Wang, Yibo Lin
2025 A conf
DiffCCD: Differentiable Concurrent Clock and Data Optimization.
ICCAD
Yuhao Ji, Yuntao Lu, Zuodong Zhang, Zizheng Guo, Yibo Lin, Bei Yu
2025 A conf
Differentiable Physical Optimization.
ICCAD
Yufan Du, Zizheng Guo, Runsheng Wang, Yibo Lin
2025 J jnl
DiffuSE: Cross-Layer Design Space Exploration of DNN Accelerator via Diffusion-Driven Optimization.
CoRR
Yi Ren, Chenhao Xue, Jiaxing Zhang, Chen Zhang, Qiang Xu, Yibo Lin, Lining Zhang, Guangyu Sun
2025 J jnl
Evolution of Optimization Algorithms for Global Placement via Large Language Models.
CoRR
Xufeng Yao, Jiaxi Jiang, Yuxuan Zhao, Peiyu Liao, Yibo Lin, Bei Yu
2025 — conf
Exploring Better Intra-Cell Routability for Layout Synthesis of Multi-Row Standard Cells.
ASP-DAC
Kairong Guo, Xiaohan Gao, Haoyi Zhang, Runsheng Wang, Ru Huang, Yibo Lin
2025 J jnl
Fast and Accurate Cross-PVT Full-Chip Leakage Power Estimation With Multi-Task Learning.
IEEE Access
Zhuomin Chai, Wei Liu, Yibo Lin, Runsheng Wang
2025 A* conf
G-SpNN: GPU-Accelerated Passivity Enforcement for S-Parameter Modeling with Neural Networks.
DAC
Lijie Zeng, Jiatai Sun, Xiao Wu, Dan Niu, Tianshi Wang, Yibo Lin, Zuochang Ye, Zhou Jin
2025 J jnl
GAP-LA: GPU-Accelerated Performance-Driven Layer Assignment.
CoRR
Chunyuan Zhao, Zizheng Guo, Zuodong Zhang, Yibo Lin
2025 A* conf
GEM: GPU-Accelerated Emulator-Inspired RTL Simulation.
DAC
Zizheng Guo, Yanqing Zhang, Runsheng Wang, Yibo Lin, Haoxing Ren
2025 A conf
GPU Acceleration for Versatile Buffer Insertion.
ICCAD
Yuan Pu, Yuhao Ji, Siying Yu, Zuodong Zhang, Zizheng Guo, Zhuolun He, Yibo Lin, David Z. Pan, Bei Yu
2025 A conf
GTA: GPU-Accelerated Track Assignment with Lightweight Lookup Table for Conflict Detection.
ICCAD
Chunyuan Zhao, Jiarui Wang, Xun Jiang, Jincheng Lou, Yibo Lin
2025 A conf
Handling Latch Loops in Timing Analysis with Improved Complexity and Divergent Loop Detection.
DATE
Xizhe Shi, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang
2025 J jnl
HeteroSTA: A CPU-GPU Heterogeneous Static Timing Analysis Engine with Holistic Industrial Design Support.
CoRR
Zizheng Guo, Haichuan Liu, Xizhe Shi, Shenglu Hua, Zuodong Zhang, Chunyuan Zhao, Runsheng Wang, Yibo Lin
2025 A conf
High-Resolution Full-Chip Thermal Resistance Extraction of BEOL Interconnects in 3-D ICs Considering Detailed Via Connectivity.
ICCAD
Tianxiang Zhu, Qipan Wang, Yibo Lin, Runsheng Wang
2025 J jnl
Imaging Scheme of Joint Processing of Boundary Array Based on Fast Convolution.
IEEE Trans. Instrum. Meas.
Yibo Lin, Hongzhi Guo, Changhao Shang, Wei Zhang, Zishu He
2025 A conf
IncreGPUSTA: GPU-Accelerated Incremental Static Timing Analysis for Iterative Design Flows.
ICCAD
Haichuan Liu, Zizheng Guo, Runsheng Wang, Yibo Lin
2025 J jnl
IncreMacro: Incremental Macro Placement Refinement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuan Pu, Tinghuan Chen, Zhuolun He, Jiajun Qin, Chen Bai, Haisheng Zheng, Yibo Lin, Bei Yu
2025 — conf
LEGALM: Efficient Legalization for Mixed-Cell-Height Circuits with Linearized Augmented Lagrangian Method.
ISPD
Jing Mai, Chunyuan Zhao, Zuodong Zhang, Zhixiong Di, Yibo Lin, Runsheng Wang, Ru Huang
2025 J jnl
LaMoSys3.5D: Enabling 3.5D-IC-Based Large Language Model Inference Serving Systems via Hardware/Software Co-Design.
CoRR
Qipan Wang, Zhe Zhang, Shuangchen Li, Hongzhong Zheng, Zheng Liang, Yibo Lin, Runsheng Wang, Ru Huang
2025 J jnl
LayoutCopilot: An LLM-Powered Multiagent Collaborative Framework for Interactive Analog Layout Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bingyang Liu, Haoyi Zhang, Xiaohan Gao, Zichen Kong, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang
2025 C conf
LayoutCopilot: LLM-Empowered Analog Layout Design towards Enhanced Human-Machine Interaction.
ISCAS
Bingyang Liu, Haoyi Zhang, Xiaohan Gao, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang
2025 J jnl
Learning placement order for constructive floorplanning.
Integr.
Weiqiang Yao, Yibo Lin, Lin Li
2025 A conf
MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs.
ICCAD
Chenchen Zhao, Zhengyuan Shi, Xiangyu Wen, Chengjie Liu, Yi Liu, Yunhao Zhou, Yuxiang Zhao, Hefei Feng, Yinan Zhu, Gwok-Waa Wan, Xin Cheng, Weiyu Chen, Yongqi Fu, Chujie Chen, Chenhao Xue, Ying Wang, Yibo Lin, Jun Yang, Ning Xu, Xi Wang, Qiang Xu
2025 J jnl
MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs.
CoRR
Chenchen Zhao, Zhengyuan Shi, Xiangyu Wen, Chengjie Liu, Yi Liu, Yunhao Zhou, Yuxiang Zhao, Hefei Feng, Yinan Zhu, Gwok-Waa Wan, Xin Cheng, Weiyu Chen, Yongqi Fu, Chujie Chen, Chenhao Xue, Guangyu Sun, Ying Wang, Yibo Lin, Jun Yang, Ning Xu, Xi Wang, Qiang Xu
2025 A conf
MORE-Stress: Model Order Reduction based Efficient Numerical Algorithm for Thermal Stress Simulation of TSV Arrays in 2.5D/3D IC.
DATE
Tianxiang Zhu, Qipan Wang, Yibo Lin, Runsheng Wang, Ru Huang
2025 A conf
Orthrus: Dual-Loop Automated Framework for System-Technology Co-Optimization.
ICCAD
Yi Ren, Baokang Peng, Chenhao Xue, Kairong Guo, Yukun Wang, Guoyao Cheng, Yibo Lin, Lining Zhang, Guangyu Sun
2025 J jnl
Orthrus: Dual-Loop Automated Framework for System-Technology Co-Optimization.
CoRR
Yi Ren, Baokang Peng, Chenhao Xue, Kairong Guo, Yukun Wang, Guoyao Cheng, Yibo Lin, Lining Zhang, Guangyu Sun
2025 J jnl
PDNNet: PDN-Aware GNN-CNN Heterogeneous Network for Dynamic IR Drop Prediction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuxiang Zhao, Zhuomin Chai, Xun Jiang, Yibo Lin, Runsheng Wang, Ru Huang
2025 — conf
PathGen: An Efficient Parallel Critical Path Generation Algorithm.
ASP-DAC
Che Chang, Boyang Zhang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yi-Hua Chung, Wan-Luan Lee, Zizheng Guo, Yibo Lin, Tsung-Wei Huang
2025 A* conf
RUPlace: Optimizing Routability via Unified Placement and Routing Formulation.
DAC
Yifan Chen, Jing Mai, Zuodong Zhang, Yibo Lin
2025 A* conf
SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation.
DAC
Ziyang Yu, Peng Xu, Zixiao Wang, Binwu Zhu, Qipan Wang, Yibo Lin, Runsheng Wang, Bei Yu, Martin D. F. Wong
2025 A conf
SEGA-DCIM: Design Space Exploration-Guided Automatic Digital CIM Compiler with Multiple Precision Support.
DATE
Haikang Diao, Haoyi Zhang, Jiahao Song, Haoyang Luo, Yibo Lin, Runsheng Wang, Yuan Wang, Xiyuan Tang
2025 J jnl
SEGA-DCIM: Design Space Exploration-Guided Automatic Digital CIM Compiler with Multiple Precision Support.
CoRR
Haikang Diao, Haoyi Zhang, Jiahao Song, Haoyang Luo, Yibo Lin, Runsheng Wang, Yuan Wang, Xiyuan Tang
2025 J jnl
Sign-Off Timing Considerations via Concurrent Routing Topology Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Siting Liu, Ziyi Wang, Fangzhou Liu, Yibo Lin, Bei Yu, Martin D. F. Wong
2025 A* conf
Synergistic Die-Level Router for Multi-FPGA System with Time-Division Multiplexing Optimization.
DAC
Jiarui Wang, Yanjing Liu, Yibo Lin
2025 J jnl
Theseus: Exploring Efficient Wafer-Scale Chip Design for Large Language Models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jingchen Zhu, Chenhao Xue, Yiqi Chen, Zhao Wang, Chen Zhang, Yu Shen, Yifan Chen, Zekang Cheng, Yu Jiang, Tianqi Wang, Yibo Lin, Wei Hu, Bin Cui, Runsheng Wang, Yun Liang, Guangyu Sun
2025 — conf
iTAP: An Incremental Task Graph Partitioner for Task-parallel Static Timing Analysis.
ASP-DAC
Boyang Zhang, Che Chang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yang Sui, Chih-Chun Chang, Yi-Hua Chung, Wan-Luan Lee, Zizheng Guo, Yibo Lin, Tsung-Wei Huang
2024 — conf
A Parallel Simulation Framework Incorporating Machine Learning-Based Hotspot Detection for Accelerated Power Grid Analysis.
MLCAD
Yangfan Jiang, Jianfei Song, Xunzhao Yin, Xiao Dong, Songyu Sun, Yibo Lin, Zhou Jin, Xiaoyu Yang, Cheng Zhuo
2024 A conf
ATPlace2.5D: Analytical Thermal-Aware Chiplet Placement Framework for Large-Scale 2.5D-IC.
ICCAD
Qipan Wang, Xueqing Li, Tianyu Jia, Yibo Lin, Runsheng Wang, Ru Huang
2024 C conf
An Efficient Task-Parallel Pipeline Programming Framework.
HPC Asia
Cheng-Hsiang Chiu, Zhicheng Xiong, Zizheng Guo, Tsung-Wei Huang, Yibo Lin
2024 J jnl
AnalogXpert: Automating Analog Topology Synthesis by Incorporating Circuit Design Expertise into Large Language Models.
CoRR
Haoyi Zhang, Shizhao Sun, Yibo Lin, Runsheng Wang, Jiang Bian
2024 J jnl
Analytical Die-to-Die 3-D Placement With Bistratal Wirelength Model and GPU Acceleration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Peiyu Liao, Yuxuan Zhao, Dawei Guo, Yibo Lin, Bei Yu
2024 J jnl
Analytical Heterogeneous Die-to-Die 3D Placement with Macros.
CoRR
Yuxuan Zhao, Peiyu Liao, Siting Liu, Jiaxi Jiang, Yibo Lin, Bei Yu
2024 — conf
Automated Lithography Resolution Enhancement with Deep Learning Enabled Layout Modification during Physical Design Stage.
ACM Great Lakes Symposium on VLSI
Zixi Liu, Yibo Lin, Xiaojing Su, Xiaohuan Ling, Xin Hong, Bojie Ma, Yajuan Su, Yayi Wei
2024 A* conf
CircuitNet 2.0: An Advanced Dataset for Promoting Machine Learning Innovations in Realistic Chip Design Environment.
ICLR
Xun Jiang, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang
2024 J jnl
Dynamic Supply Noise Aware Timing Analysis With JIT Machine Learning Integration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yufei Chen, Zizheng Guo, Runsheng Wang, Ru Huang, Yibo Lin, Cheng Zhuo
2024 A* conf
EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration.
DAC
Haoyi Zhang, Jiahao Song, Xiaohan Gao, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang
2024 J jnl
EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration.
CoRR
Haoyi Zhang, Jiahao Song, Xiaohan Gao, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang
2024 J jnl
Erratum to: Large circuit models: opportunities and challenges.
Sci. China Inf. Sci.
Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Ru Huang, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yu Li, Yun Liang, Jinwei Liu, Yi Liu, Yibo Lin, Guojie Luo, Hongyang Pan, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Junchi Yan, Jun Yang, Bei Yu, Mingxuan Yuan, Evangeline F. Y. Young, Xuan Zeng, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
2024 A conf
FaStTherm: Fast and Stable Full-Chip Transient Thermal Predictor Considering Nonlinear Effects.
ICCAD
Tianxiang Zhu, Qipan Wang, Yibo Lin, Runsheng Wang, Ru Huang
2024 — conf
First Experimental Demonstration of Self-Aligned Flip FET (FFET): A Breakthrough Stacked Transistor Technology with 2.5T Design, Dual-Side Active and Interconnects.
VLSI Technology and Circuits
Haoran Lu, Yandong Ge, Xun Jiang, Jiacheng Sun, Wanyue Peng, Rui Guo, Ming Li, Yibo Lin, Runsheng Wang, Heng Wu, Ru Huang
2024 A conf
Fusion of Global Placement and Gate Sizing with Differentiable Optimization.
ICCAD
Yufan Du, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang
2024 A* conf
G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner.
DAC
Wan-Luan Lee, Dian-Lun Lin, Tsung-Wei Huang, Shui Jiang, Tsung-Yi Ho, Yibo Lin, Bei Yu
2024 A conf
HeLEM-GR: Heterogeneous Global Routing with Linearized Exponential Multiplier Method.
ICCAD
Chunyuan Zhao, Zizheng Guo, Rui Wang, Zaiwen Wen, Yun Liang, Yibo Lin
2024 A* conf
Hestia: An Efficient Cross-Level Debugger for High-Level Synthesis.
MICRO
Ruifan Xu, Jin Luo, Yawen Zhang, Yibo Lin, Runsheng Wang, Ru Huang, Yun Liang
2024 A conf
HeteroExcept: A CPU-GPU Heterogeneous Algorithm to Accelerate Exception-aware Static Timing Analysis.
ICCAD
Zizheng Guo, Zuodong Zhang, Wuxi Li, Tsung-Wei Huang, Xizhe Shi, Yufan Du, Yibo Lin, Runsheng Wang, Ru Huang
2024 A conf
Heterogeneous Static Timing Analysis with Advanced Delay Calculator.
DATE
Zizheng Guo, Tsung-Wei Huang, Zhou Jin, Cheng Zhuo, Yibo Lin, Runsheng Wang, Ru Huang
2024 J jnl
Imbalanced Large Graph Learning Framework for FPGA Logic Elements Packing Prediction.
IEEE Trans. Circuits Syst. II Express Briefs
Zhixiong Di, Runzhe Tao, Lin Chen, Qiang Wu, Yibo Lin
2024 — conf
IncreMacro: Incremental Macro Placement Refinement.
ISPD
Yuan Pu, Tinghuan Chen, Zhuolun He, Chen Bai, Haisheng Zheng, Yibo Lin, Bei Yu
2024 A conf
Joint Placement Optimization for Hierarchical Analog/Mixed-Signal Circuits.
ICCAD
Xiaohan Gao, Haoyi Zhang, Bingyang Liu, Yibo Lin, Runsheng Wang, Ru Huang
2024 J jnl
LEAPS: Topological-Layout-Adaptable Multi-Die FPGA Placement for Super Long Line Minimization.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhixiong Di, Runzhe Tao, Jing Mai, Lin Chen, Yibo Lin
2024 J jnl
Large circuit models: opportunities and challenges.
Sci. China Inf. Sci.
Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Ru Huang, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yu Li, Yun Liang, Jinwei Liu, Yi Liu, Yibo Lin, Guojie Luo, Hongyang Pan, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Junchi Yan, Jun Yang, Bei Yu, Mingxuan Yuan, Evangeline F. Y. Young, Xuan Zeng, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
2024 J jnl
LayoutCopilot: An LLM-powered Multi-agent Collaborative Framework for Interactive Analog Layout Design.
CoRR
Bingyang Liu, Haoyi Zhang, Xiaohan Gao, Zichen Kong, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang
2024 A* conf
Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs.
DAC
Yuan Pu, Fangzhou Liu, Yu Zhang, Zhuolun He, Yibo Lin, Kai-Yuan Chao, Bei Yu
2024 J jnl
MORE-Stress: Model Order Reduction based Efficient Numerical Algorithm for Thermal Stress Simulation of TSV Arrays in 2.5D/3D IC.
CoRR
Tianxiang Zhu, Qipan Wang, Yibo Lin, Runsheng Wang, Ru Huang
2024 A conf
MORPH: More Robust ASIC Placement for Hybrid Region Constraint Management.
ICCAD
Jing Mai, Zuodong Zhang, Yibo Lin, Runsheng Wang, Ru Huang
2024 — conf
Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells.
ISPD
Yu Zhang, Yuan Pu, Fangzhou Liu, Peiyu Liao, Kai-Yuan Chao, Keren Zhu, Yibo Lin, Bei Yu
2024 J jnl
Multielectrostatic FPGA Placement Considering SLICEL-SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jing Mai, Jiarui Wang, Zhixiong Di, Yibo Lin
2024 A* conf
Oltron: Algorithm-Hardware Co-design for Outlier-Aware Quantization of LLMs with Inter-/Intra-Layer Adaptation.
DAC
Chenhao Xue, Chen Zhang, Xun Jiang, Zhutianya Gao, Yibo Lin, Guangyu Sun
2024 J jnl
PDNNet: PDN-Aware GNN-CNN Heterogeneous Network for Dynamic IR Drop Prediction.
CoRR
Yuxiang Zhao, Zhuomin Chai, Xun Jiang, Yibo Lin, Runsheng Wang, Ru Huang
2024 A* conf
PVTSizing: A TuRBO-RL-Based Batch-Sampling Optimization Framework for PVT-Robust Analog Circuit Synthesis.
DAC
Zichen Kong, Xiyuan Tang, Wei Shi, Yiheng Du, Yibo Lin, Yuan Wang
2024 J jnl
Post-layout simulation driven analog circuit sizing.
Sci. China Inf. Sci.
Xiaohan Gao, Haoyi Zhang, Siyuan Ye, Mingjie Liu, David Z. Pan, Linxiao Shen, Runsheng Wang, Yibo Lin, Ru Huang
2024 A* conf
PowPrediCT: Cross-Stage Power Prediction with Circuit-Transformation-Aware Learning.
DAC
Yufan Du, Zizheng Guo, Xun Jiang, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang
2024 — ed.
Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, MLCAD 2024, Salt Lake City, UT, USA, September 9-11, 2024
MLCAD
Hussam Amrouch, Jiang Hu, Siddharth Garg, Yibo Lin
2024 — conf
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs.
ISPD
Siting Liu, Jiaxi Jiang, Zhuolun He, Ziyi Wang, Yibo Lin, Bei Yu, Martin D. F. Wong
2024 A conf
SAGERoute 2.0: Hierarchical Analog and Mixed Signal Routing Considering Versatile Routing Scenarios.
DATE
Haoyi Zhang, Xiaohan Gao, Zilong Shen, Jiahao Song, Xiaoxu Cheng, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang
2024 J jnl
The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models.
CoRR
Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yun Liang, Yibo Lin, Jinwei Liu, Yi Liu, Guojie Luo, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Evangeline F. Y. Young, Bei Yu, Mingxuan Yuan, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
2024 A* conf
Top-Level Routing for Multiply-Instantiated Blocks with Topology Hashing.
DAC
Jiarui Wang, Xun Jiang, Yibo Lin
2023 J jnl
A GPU-Accelerated Framework for Path-Based Timing Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Guannan Guo, Tsung-Wei Huang, Yibo Lin, Zizheng Guo, Sushma Yellapragada, Martin D. F. Wong
2023 — conf
A Robust FPGA Router with Concurrent Intra-CLB Rerouting.
ASP-DAC
Jiarui Wang, Jing Mai, Zhixiong Di, Yibo Lin
2023 J jnl
AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Error-Efficient Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zuodong Zhang, Zizheng Guo, Yibo Lin, Meng Li, Runsheng Wang, Ru Huang
2023 J jnl
Accelerating Static Timing Analysis Using CPU-GPU Heterogeneous Parallelism.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zizheng Guo, Tsung-Wei Huang, Yibo Lin
2023 J jnl
Analytical Die-to-Die 3D Placement with Bistratal Wirelength Model and GPU Acceleration.
CoRR
Peiyu Liao, Yuxuan Zhao, Dawei Guo, Yibo Lin, Bei Yu
2023 J jnl
CircuitNet: An Open-Source Dataset for Machine Learning in VLSI CAD Applications With Improved Domain-Specific Evaluation Metric and Learning Strategies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhuomin Chai, Yuxiang Zhao, Wei Liu, Yibo Lin, Runsheng Wang, Ru Huang
2023 A* conf
Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement.
DAC
Siting Liu, Ziyi Wang, Fangzhou Liu, Yibo Lin, Bei Yu, Martin D. F. Wong
2023 J jnl
DRC-SG 2.0: Efficient Design Rule Checking Script Generation via Key Information Extraction.
ACM Trans. Design Autom. Electr. Syst.
Binwu Zhu, Xinyun Zhang, Yibo Lin, Bei Yu, Martin D. F. Wong
2023 J jnl
DREAMPlace 4.0: Timing-Driven Placement With Momentum-Based Net Weighting and Lagrangian-Based Refinement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Peiyu Liao, Dawei Guo, Zizheng Guo, Siting Liu, Yibo Lin, Bei Yu
2023 J jnl
Efficient Aging-Aware Standard Cell Library Characterization Based on Sensitivity Analysis.
IEEE Trans. Circuits Syst. II Express Briefs
Xinfa Zhang, Zuodong Zhang, Yibo Lin, Zhigang Ji, Runsheng Wang, Ru Huang
2023 J jnl
FastGR: Global Routing on CPU-GPU With Heterogeneous Task Graph Scheduler.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Siting Liu, Yuan Pu, Peiyu Liao, Hongzhong Wu, Rui Zhang, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu
2023 A* conf
FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler (Extended Abstract).
IJCAI
Siting Liu, Yuan Pu, Peiyu Liao, Hongzhong Wu, Rui Zhang, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu
2023 A* conf
General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism.
DAC
Zizheng Guo, Zuodong Zhang, Xun Jiang, Wuxi Li, Yibo Lin, Runsheng Wang, Ru Huang
2023 J jnl
HybridNet: Dual-Branch Fusion of Geometrical and Topological Views for VLSI Congestion Prediction.
CoRR
Yuxiang Zhao, Zhuomin Chai, Yibo Lin, Runsheng Wang, Ru Huang
2023 J jnl
Imbalanced Large Graph Learning Framework for FPGA Logic Elements Packing Prediction.
CoRR
Zhixiong Di, Runzhe Tao, Lin Chen, Qiang Wu, Yibo Lin
2023 J jnl
Interactive Analog Layout Editing With Instant Placement and Routing Legalization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaohan Gao, Haoyi Zhang, Mingjie Liu, Linxiao Shen, David Z. Pan, Yibo Lin, Runsheng Wang, Ru Huang
2023 J jnl
Introduction to the Special Issue on Machine Learning for CAD/EDA.
ACM Trans. Design Autom. Electr. Syst.
Yibo Lin, Avi Ziv, Haoxing Ren
2023 A conf
Invited Paper: Accelerating Routability and Timing Optimization with Open-Source AI4EDA Dataset CircuitNet and Heterogeneous Platforms.
ICCAD
Xun Jiang, Zizheng Guo, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang
2023 A* conf
Khronos: Fusing Memory Access for Improved Hardware RTL Simulation.
MICRO
Kexing Zhou, Yun Liang, Yibo Lin, Runsheng Wang, Ru Huang
2023 J jnl
LEAPS: Topological-Layout-Adaptable Multi-die FPGA Placement for Super Long Line Minimization.
CoRR
Zhixiong Di, Runzhe Tao, Jing Mai, Lin Chen, Yibo Lin
2023 A* conf
LRSDP: Low-Rank SDP for Triple Patterning Lithography Layout Decomposition.
DAC
Yu Zhang, Yifan Chen, Zhonglin Xie, Hong Xu, Zaiwen Wen, Yibo Lin, Bei Yu
2023 A* conf
MTL-Designer: An Integrated Flow for Analysis and Synthesis of Microstrip Transmission Line.
DAC
Qipan Wang, Ping Liu, Liguo Jiang, Mingjie Liu, Yibo Lin, Runsheng Wang, Ru Huang
2023 — conf
MacroRank: Ranking Macro Placement Solutions Leveraging Translation Equivariancy.
ASP-DAC
Yifan Chen, Jing Mai, Xiaohan Gao, Muhan Zhang, Yibo Lin
2023 A* conf
Mitigating Distribution Shift for Congestion Optimization in Global Placement.
DAC
Su Zheng, Lancheng Zou, Siting Liu, Yibo Lin, Bei Yu, Martin D. F. Wong
2023 J jnl
Multi-Electrostatic FPGA Placement Considering SLICEL-SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization.
CoRR
Jing Mai, Jiarui Wang, Zhixiong Di, Yibo Lin
2023 A* conf
On a Moreau Envelope Wirelength Model for Analytical Global Placement.
DAC
Peiyu Liao, Hongduo Liu, Yibo Lin, Bei Yu, Martin D. F. Wong
2023 — conf
OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit.
ASICON
Jing Mai, Jiarui Wang, Zhixiong Di, Guojie Luo, Yun Liang, Yibo Lin
2023 J jnl
OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit.
CoRR
Jing Mai, Jiarui Wang, Zhixiong Di, Guojie Luo, Yun Liang, Yibo Lin
2023 J jnl
Post-Layout Simulation Driven Analog Circuit Sizing.
CoRR
Xiaohan Gao, Haoyi Zhang, Siyuan Ye, Mingjie Liu, David Z. Pan, Linxiao Shen, Runsheng Wang, Yibo Lin, Ru Huang
2023 A conf
READ: Reliability-Enhanced Accelerator Dataflow Optimization Using Critical Input Pattern Reduction.
ICCAD
Zuodong Zhang, Renjie Wei, Meng Li, Yibo Lin, Runsheng Wang, Ru Huang
2023 A conf
READ: Reliability-Enhanced Accelerator Dataflow Optimization using Critical Input Pattern Reduction.
DATE
Zuodong Zhang, Meng Li, Yibo Lin, Runsheng Wang, Ru Huang
2023 J jnl
READ: Reliability-Enhanced Accelerator Dataflow Optimization using Critical Input Pattern Reduction.
CoRR
Zuodong Zhang, Renjie Wei, Meng Li, Yibo Lin, Runsheng Wang, Ru Huang
2023 A conf
SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility.
DATE
Haoyi Zhang, Xiaohan Gao, Haoyang Luo, Jiahao Song, Xiyuan Tang, Junhua Liu, Yibo Lin, Runsheng Wang, Ru Huang
2023 A conf
Stronger Mixed-Size Placement Backbone Considering Second-Order Information.
ICCAD
Yifan Chen, Zaiwen Wen, Yun Liang, Yibo Lin
2022 J jnl
A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zizheng Guo, Mingwei Yang, Tsung-Wei Huang, Yibo Lin
2022 — conf
A Tale of EDA's Long Tail: Long-Tailed Distribution Learning for Electronic Design Automation.
MLCAD
Zixuan Jiang, Mingjie Liu, Zizheng Guo, Shuhan Zhang, Yibo Lin, David Z. Pan
2022 A* conf
A timing engine inspired graph neural network model for pre-routing slack prediction.
DAC
Zizheng Guo, Mingjie Liu, Jiaqi Gu, Shuhan Zhang, David Z. Pan, Yibo Lin
2022 A* conf
AVATAR: an aging- and variation-aware dynamic timing analyzer for application-based DVAFS.
DAC
Zuodong Zhang, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang
2022 J jnl
Adaptive Layout Decomposition With Graph Embedding Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wei Li, Yuzhe Ma, Yibo Lin, Bei Yu
2022 J jnl
Asynchronous Reinforcement Learning Framework and Knowledge Transfer for Net-Order Exploration in Detailed Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yibo Lin, Tong Qu, Zongqing Lu, Yajuan Su, Yayi Wei
2022 J jnl
CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA).
CoRR
Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Wei Liu, Runsheng Wang, Ru Huang
2022 J jnl
CircuitNet: an open-source dataset for machine learning applications in electronic design automation (EDA).
Sci. China Inf. Sci.
Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Wei Liu, Runsheng Wang, Ru Huang
2022 — conf
Concurrent CPU-GPU Task Programming using Modern C++.
IPDPS Workshops
Tsung-Wei Huang, Yibo Lin
2022 J jnl
Concurrent CPU-GPU Task Programming using Modern C++.
CoRR
Tsung-Wei Huang, Yibo Lin
2022 A conf
DREAMPlace 4.0: Timing-driven Global Placement with Momentum-based Net Weighting.
DATE
Peiyu Liao, Siting Liu, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu
2022 A conf
DeePEB: A Neural Partial Differential Equation Solver for Post Exposure Baking Simulation in Lithography.
ICCAD
Qipan Wang, Xiaohan Gao, Yibo Lin, Runsheng Wang, Ru Huang
2022 A* conf
Differentiable-timing-driven global placement.
DAC
Zizheng Guo, Yibo Lin
2022 — conf
Efficient Critical Paths Search Algorithm using Mergeable Heap.
ASP-DAC
Kexing Zhou, Zizheng Guo, Tsung-Wei Huang, Yibo Lin
2022 — conf
Efficient Design Rule Checking Script Generation via Key Information Extraction.
MLCAD
Binwu Zhu, Xinyun Zhang, Yibo Lin, Bei Yu, Martin D. F. Wong
2022 A conf
EventTimer: Fast and Accurate Event-Based Dynamic Timing Analysis.
DATE
Zuodong Zhang, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang
2022 — conf
FPGA-Accelerated Maze Routing Kernel for VLSI Designs.
ASP-DAC
Xun Jiang, Jiarui Wang, Yibo Lin, Zhongfeng Wang
2022 A conf
FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler.
DATE
Siting Liu, Peiyu Liao, Rui Zhang, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu
2022 A conf
GPU-Accelerated Rectilinear Steiner Tree Generation.
ICCAD
Zizheng Guo, Feng Gu, Yibo Lin
2022 J jnl
LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction.
CoRR
Bowen Wang, Guibao Shen, Dong Li, Jianye Hao, Wulong Liu, Yu Huang, Hongzhong Wu, Yibo Lin, Guangyong Chen, Pheng-Ann Heng
2022 A* conf
LHNN: lattice hypergraph neural network for VLSI congestion prediction.
DAC
Bowen Wang, Guibao Shen, Dong Li, Jianye Hao, Wulong Liu, Yu Huang, Hongzhong Wu, Yibo Lin, Guangyong Chen, Pheng-Ann Heng
2022 J jnl
MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Martin Rapp, Hussam Amrouch, Yibo Lin, Bei Yu, David Z. Pan, Marilyn Wolf, Jörg Henkel
2022 A conf
Mixed-Cell-Height Legalization on CPU-GPU Heterogeneous Systems.
DATE
Haoyu Yang, Kit Fung, Yuxuan Zhao, Yibo Lin, Bei Yu
2022 A* conf
Multi-electrostatic FPGA placement considering SLICEL-SLICEM heterogeneity and clock feasibility.
DAC
Jing Mai, Yibai Meng, Zhixiong Di, Yibo Lin
2022 J jnl
Pipeflow: An Efficient Task-Parallel Pipeline Programming Framework using Modern C++.
CoRR
Cheng-Hsiang Chiu, Tsung-Wei Huang, Zizheng Guo, Yibo Lin
2022 J jnl
Taskflow: A General-Purpose Parallel and Heterogeneous Task Programming System.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tsung-Wei Huang, Dian-Lun Lin, Yibo Lin, Chun-Xun Lin
2022 J jnl
Taskflow: A Lightweight Parallel and Heterogeneous Task Graph Computing System.
IEEE Trans. Parallel Distributed Syst.
Tsung-Wei Huang, Dian-Lun Lin, Chun-Xun Lin, Yibo Lin
2022 J jnl
Towards Machine Learning for Placement and Routing in Chip Design: a Methodological Overview.
CoRR
Junchi Yan, Xianglong Liu, Ruoyu Cheng, Yibo Lin
2022 J jnl
elfPlace: Electrostatics-Based Placement for Large-Scale Heterogeneous FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yibai Meng, Wuxi Li, Yibo Lin, David Z. Pan
2021 J jnl
A Novel and Unified Full-Chip CMP Model Aware Dummy Fill Insertion Framework With SQP-Based Optimization Method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Junzhe Cai, Changhao Yan, Yudong Tao, Yibo Lin, Sheng-Guo Wang, David Z. Pan, Xuan Zeng
2021 A* conf
A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs.
DAC
Zizheng Guo, Tsung-Wei Huang, Yibo Lin
2021 — conf
Asynchronous Multi-Nets Detailed Routing in VLSI using Multi-Agent Reinforcement Learning.
IC-NIDC
Xuhua Ju, Konglin Zhu, Yibo Lin, Lin Zhang
2021 A conf
Asynchronous Reinforcement Learning Framework for Net Order Exploration in Detailed Routing.
DATE
Tong Qu, Yibo Lin, Zongqing Lu, Yajuan Su, Yayi Wei
2021 J jnl
Cpp-Taskflow: A General-Purpose Parallel Task Programming System at Scale.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tsung-Wei Huang, Yibo Lin, Chun-Xun Lin, Guannan Guo, Martin D. F. Wong
2021 J jnl
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yibo Lin, Zixuan Jiang, Jiaqi Gu, Wuxi Li, Shounak Dhar, Haoxing Ren, Brucek Khailany, David Z. Pan
2021 — conf
Deep Learning for Mask Synthesis and Verification: A Survey.
ASP-DAC
Yibo Lin
2021 J jnl
GAN-SRAF: Subresolution Assist Feature Generation Using Generative Adversarial Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mohamed Baker Alawieh, Yibo Lin, Zaiwei Zhang, Meng Li, Qixing Huang, David Z. Pan
2021 A conf
GPU-accelerated Critical Path Generation with Path Constraints.
ICCAD
Guannan Guo, Tsung-Wei Huang, Yibo Lin, Martin D. F. Wong
2021 A* conf
GPU-accelerated Path-based Timing Analysis.
DAC
Guannan Guo, Tsung-Wei Huang, Yibo Lin, Martin D. F. Wong
2021 A conf
Global Placement with Deep Learning-Enabled Explicit Routability Optimization.
DATE
Siting Liu, Qi Sun, Peiyu Liao, Yibo Lin, Bei Yu
2021 A conf
HeteroCPPR: Accelerating Common Path Pessimism Removal with Heterogeneous CPU-GPU Parallelism.
ICCAD
Zizheng Guo, Tsung-Wei Huang, Yibo Lin
2021 A* conf
Interactive Analog Layout Editing with Instant Placement Legalization.
DAC
Xiaohan Gao, Mingjie Liu, David Z. Pan, Yibo Lin
2021 — conf
Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks.
ASP-DAC
Xiaohan Gao, Chenhui Deng, Mingjie Liu, Zhiru Zhang, David Z. Pan, Yibo Lin
2021 J jnl
MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII.
IEEE Des. Test
Hao Chen, Mingjie Liu, Biying Xu, Keren Zhu, Xiyuan Tang, Shaolan Li, Yibo Lin, Nan Sun, David Z. Pan
2021 J jnl
OpenMPL: An Open-Source Layout Decomposer.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wei Li, Yuzhe Ma, Qi Sun, Lu Zhang, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan
2021 — conf
Physical Synthesis for Advanced Neural Network Processors.
ASP-DAC
Zhuolun He, Peiyu Liao, Siting Liu, Yuzhe Ma, Yibo Lin, Bei Yu
2021 A conf
Towards AQFP-Capable Physical Design Automation.
DATE
Hongjia Li, Mengshu Sun, Tianyun Zhang, Olivia Chen, Nobuyuki Yoshikawa, Bei Yu, Yanzhi Wang, Yibo Lin
2021 A* conf
Ultrafast CPU/GPU Kernels for Density Accumulation in Placement.
DAC
Zizheng Guo, Jing Mai, Yibo Lin
2020 J jnl
ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yibo Lin, Wuxi Li, Jiaqi Gu, Haoxing Ren, Brucek Khailany, David Z. Pan
2020 A* conf
Adaptive Layout Decomposition with Graph Embedding Neural Networks.
DAC
Wei Li, Jialu Xia, Yuzhe Ma, Jialu Li, Yibo Lin, Bei Yu
2020 J jnl
Cpp-Taskflow v2: A General-purpose Parallel and Heterogeneous Task Programming System at Scale.
CoRR
Tsung-Wei Huang, Dian-Lun Lin, Yibo Lin, Chun-Xun Lin
2020 A conf
DREAMPlace 3.0: Multi-Electrostatics Based Robust VLSI Placement with Region Constraints.
ICCAD
Jiaqi Gu, Zixuan Jiang, Yibo Lin, David Z. Pan
2020 A conf
GPU Acceleration in VLSI Back-end Design: Overview and Case Studies.
ICCAD
Yibo Lin
2020 A conf
GPU-Accelerated Static Timing Analysis.
ICCAD
Zizheng Guo, Tsung-Wei Huang, Yibo Lin
2020 — conf
High-Definition Routing Congestion Prediction for Large-Scale FPGAs.
ASP-DAC
Mohamed Baker Alawieh, Wuxi Li, Yibo Lin, Love Singhal, Mahesh A. Iyer, David Z. Pan
2020 J jnl
Powernet: SOI Lateral Power Device Breakdown Prediction With Deep Neural Networks.
IEEE Access
Jing Chen, Mohamed Baker Alawieh, Yibo Lin, Maolin Zhang, Jun Zhang, Yufeng Guo, David Z. Pan
2020 — conf
ReGDS: A Reverse Engineering Framework from GDSII to Gate-level Netlist.
HOST
Rachel Selina Rajarathnam, Yibo Lin, Yier Jin, David Z. Pan
2020 — conf
S
ASP-DAC
Mingjie Liu, Wuxi Li, Keren Zhu, Biying Xu, Yibo Lin, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan
2020 J jnl
Semisupervised Hotspot Detection With Self-Paced Multitask Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ying Chen, Yibo Lin, Tianyang Gai, Yajuan Su, Yayi Wei, David Z. Pan
2020 — conf
TEMPO: Fast Mask Topography Effect Modeling with Deep Learning.
ISPD
Wei Ye, Mohamed Baker Alawieh, Yuki Watanabe, Shigeki Nojima, Yibo Lin, David Z. Pan
2019 J jnl
A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Meng Li, Bei Yu, Yibo Lin, Xiaoqing Xu, Wuxi Li, David Z. Pan
2019 A* conf
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.
DAC
Yibo Lin, Shounak Dhar, Wuxi Li, Haoxing Ren, Brucek Khailany, David Z. Pan
2019 J jnl
Data Efficient Lithography Modeling With Transfer Learning and Active Data Selection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yibo Lin, Meng Li, Yuki Watanabe, Taiki Kimura, Tetsuaki Matsunawa, Shigeki Nojima, David Z. Pan
2019 — conf
Device Layer-Aware Analytical Placement for Analog Circuits.
ISPD
Biying Xu, Shaolan Li, Chak-Wa Pui, Derong Liu, Linxiao Shen, Yibo Lin, Nan Sun, David Z. Pan
2019 A* conf
GAN-SRAF: Sub-Resolution Assist Feature Generation Using Conditional Generative Adversarial Networks.
DAC
Mohamed Baker Alawieh, Yibo Lin, Zaiwei Zhang, Meng Li, Qixing Huang, David Z. Pan
2019 A conf
GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance.
ICCAD
Keren Zhu, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan
2019 A conf
Litho-GPA: Gaussian Process Assurance for Lithography Hotspot Detection.
DATE
Wei Ye, Mohamed Baker Alawieh, Meng Li, Yibo Lin, David Z. Pan
2019 A* conf
LithoGAN: End-to-End Lithography Modeling with Generative Adversarial Networks.
DAC
Wei Ye, Mohamed Baker Alawieh, Yibo Lin, David Z. Pan
2019 — conf
LithoROC: lithography hotspot detection with explicit ROC optimization.
ASP-DAC
Wei Ye, Yibo Lin, Meng Li, Qiang Liu, David Z. Pan
2019 A conf
MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper.
ICCAD
Biying Xu, Keren Zhu, Mingjie Liu, Yibo Lin, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan
2019 A conf
Mixed Precision Neural Architecture Search for Energy Efficient Deep Learning.
ICCAD
Chengyue Gong, Zixuan Jiang, Dilin Wang, Yibo Lin, Qiang Liu, David Z. Pan
2019 — conf
OpenMPL: An Open Source Layout Decomposer: Invited Paper.
ASICON
Wei Li, Yuzhe Ma, Qi Sun, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan
2019 — conf
Semi-supervised hotspot detection with self-paced multi-task learning.
ASP-DAC
Ying Chen, Yibo Lin, Tianyang Gai, Yajuan Su, Yayi Wei, David Z. Pan
2019 — conf
Tackling signal electromigration with learning-based detection and multistage mitigation.
ASP-DAC
Wei Ye, Mohamed Baker Alawieh, Yibo Lin, David Z. Pan
2019 A conf
Towards a Theoretical Understanding of Hashing-Based Neural Nets.
AISTATS
Yibo Lin, Zhao Song, Lin F. Yang
2019 A* conf
WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout.
DAC
Biying Xu, Yibo Lin, Xiyuan Tang, Shaolan Li, Linxiao Shen, Nan Sun, David Z. Pan
2019 A conf
elfPlace: Electrostatics-based Placement for Large-Scale Heterogeneous FPGAs.
ICCAD
Wuxi Li, Yibo Lin, David Z. Pan
2018 — conf
A practical split manufacturing framework for Trojan prevention via simultaneous wire lifting and cell insertion.
ASP-DAC
Meng Li, Bei Yu, Yibo Lin, Xiaoqing Xu, Wuxi Li, David Z. Pan
2018 — conf
Data Efficient Lithography Modeling with Residual Neural Networks and Transfer Learning.
ISPD
Yibo Lin, Yuki Watanabe, Taiki Kimura, Tetsuaki Matsunawa, Shigeki Nojima, Meng Li, David Z. Pan
2018 J jnl
Data Efficient Lithography Modeling with Transfer Learning and Active Data Selection.
CoRR
Yibo Lin, Meng Li, Yuki Watanabe, Taiki Kimura, Tetsuaki Matsunawa, Shigeki Nojima, David Z. Pan
2018 J jnl
Layout Synthesis for Topological Quantum Circuits With 1-D and 2-D Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yibo Lin, Bei Yu, Meng Li, David Z. Pan
2018 — conf
Layout-dependent aging mitigation for critical path timing.
ASP-DAC
Che-Lun Hsu, Shaofeng Guo, Yibo Lin, Xiaoqing Xu, Meng Li, Runsheng Wang, Ru Huang, David Z. Pan
2018 A* conf
Learning Long Term Dependencies via Fourier Recurrent Units.
ICML
Jiong Zhang, Yibo Lin, Zhao Song, Inderjit S. Dhillon
2018 J jnl
Learning Long Term Dependencies via Fourier Recurrent Units.
CoRR
Jiong Zhang, Yibo Lin, Zhao Song, Inderjit S. Dhillon
2018 A conf
Machine Learning for Yield Learning and Optimization.
ITC
Yibo Lin, Mohamed Baker Alawieh, Wei Ye, David Z. Pan
2018 J jnl
MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan
2018 J jnl
OpenMPL: An Open Source Layout Decomposer.
CoRR
Qi Sun, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan
2018 J jnl
Subresolution Assist Feature Generation With Supervised Data Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaoqing Xu, Yibo Lin, Meng Li, Tetsuaki Matsunawa, Shigeki Nojima, Chikaaki Kodama, Toshiya Kotani, David Z. Pan
2018 J jnl
Towards a Theoretical Understanding of Hashing-Based Neural Nets.
CoRR
Yibo Lin, Zhao Song, Lin F. Yang
2018 J jnl
UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine.
ACM Trans. Design Autom. Electr. Syst.
Wuxi Li, Yibo Lin, Meng Li, Shounak Dhar, David Z. Pan
2017 A* conf
Concurrent Pin Access Optimization for Unidirectional Routing.
DAC
Xiaoqing Xu, Yibo Lin, Vinicius S. Livramento, David Z. Pan
2017 — conf
DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment.
ISPD
Jiaojiao Ou, Bei Yu, Xiaoqing Xu, Joydeep Mitra, Yibo Lin, David Z. Pan
2017 J jnl
High Performance Dummy Fill Insertion With Coupling and Uniformity Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yibo Lin, Bei Yu, David Z. Pan
2017 C conf
Patterning Aware Design Optimization of Selective Etching in N5 and Beyond.
ICCD
Yibo Lin, Peter Debacker, Darko Trivkovic, Ryoung-Han Kim, Praveen Raghavan, David Z. Pan
2017 A conf
Placement mitigation techniques for power grid electromigration.
ISLPED
Wei Ye, Yibo Lin, Xiaoqing Xu, Wuxi Li, Yiwei Fu, Yongsheng Sun, Canhui Zhan, David Z. Pan
2017 J jnl
Redundant Local-Loop Insertion for Unidirectional Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaoqing Xu, Yibo Lin, Meng Li, Jiaojiao Ou, Brian Cline, David Z. Pan
2017 J jnl
Stitch aware detailed placement for multiple E-beam lithography.
Integr.
Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, David Z. Pan
2017 J jnl
Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yibo Lin, Bei Yu, Biying Xu, David Z. Pan
2016 A conf
A novel unified dummy fill insertion framework with SQP-based optimization method.
ICCAD
Yudong Tao, Changhao Yan, Yibo Lin, Sheng-Guo Wang, David Z. Pan, Xuan Zeng
2016 J jnl
Design for manufacturability and reliability in extreme-scaling VLSI.
Sci. China Inf. Sci.
Bei Yu, Xiaoqing Xu, Subhendu Roy, Yibo Lin, Jiaojiao Ou, David Z. Pan
2016 A conf
MrDP: multiple-row detailed placement of heterogeneous-sized cells for advanced nodes.
ICCAD
Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan
2016 — conf
Stitch aware detailed placement for multiple e-beam lithography.
ASP-DAC
Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, David Z. Pan
2015 A* conf
High performance dummy fill insertion with coupling and uniformity constraints.
DAC
Yibo Lin, Bei Yu, David Z. Pan
2015 J jnl
Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Yibo Lin, Zhuo Li, Charles J. Alpert, David Z. Pan
2015 A* conf
Pushing multiple patterning in sub-10nm: are we ready?
DAC
David Z. Pan, Lars Liebmann, Bei Yu, Xiaoqing Xu, Yibo Lin
2015 A conf
Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict.
ICCAD
Yibo Lin, Bei Yu, Biying Xu, David Z. Pan
2010 J jnl
The Daktari: An interactive, multi-media tool for knowledge transfer among poor livestock keepers in Kenya.
Comput. Educ.
Louise Nielsen, Claire Heffernan, Yibo Lin, Jun Yu
2009 J jnl
Addressing Animal Health Knowledge Gaps in Southern Countries: The Creation of a 2D Animal Health Resource Room.
Electron. J. Inf. Syst. Dev. Ctries.
Yibo Lin, Claire Heffernan
2009 C conf
Creating a mobile-phone based geographic surveillance system for avian influenza.
ICTD
Yibo Lin, Claire Heffernan