Yiannakis Sazeides

74 papers A* 16A 9B 7C 3Journal 29Unranked 10

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	The Non-Predictability of Mispredicted Branches using Timing Information. CoRR Ioannis Constantinou, Arthur Perais, Yiannakis Sazeides
2025	J	`jnl`	An opportunity to improve Data Center Efficiency: Optimizing the Server's Upgrade Cycle. CoRR Panagiota Nikolaou, Freddy Gabbay, Jawad Haj-Yahya, Yiannakis Sazeides
2025	J	`jnl`	Analyzing a Two-Tier Disaggregated Memory Protection Scheme Based on Memory Replication. CoRR Haris Volos, Yiannakis Sazeides
2025	J	`jnl`	How long can you sleep? Idle Time System Inefficiencies and Opportunities. CoRR Georgia Antoniou, Haris Volos, Jawad Haj-Yahya, Yiannakis Sazeides
2025	A*	`conf`	Leveraging control-flow similarity to reduce branch predictor cold effects in microservices. ISCA Haris Volos, Stylianos Vassiliou, Georgia Antoniou, Davide Basilio Bartolini, Yiannakis Sazeides
2025	B	`conf`	SAGA: A Surrogate Assisted Genetic Algorithm for Fast CPU Power Virus Generation. ISPASS Panteleimonas Chatzimiltis, Georgia Antoniou, Haris Volos, Yiannakis Sazeides
2024	J	`jnl`	Agile C-states: A Core C-state Architecture for Latency Critical Applications Optimizing both Transition and Cold-Start Latency. ACM Trans. Archit. Code Optim. Georgia Antoniou, Davide B. Bartolini, Haris Volos, Marios Kleanthous, Zhe Wang, Kleovoulos Kalaitzidis, Tom Rollet, Ziwei Li, Onur Mutlu, Yiannakis Sazeides, Jawad Haj-Yahya
2024	—	`conf`	Taming Performance Variability caused by Client-Side Hardware Configuration. IISWC Georgia Antoniou, Haris Volos, Yiannakis Sazeides
2024	J	`jnl`	Taming Performance Variability caused by Client-Side Hardware Configuration. CoRR Georgia Antoniou, Haris Volos, Yiannakis Sazeides
2022	J	`jnl`	A Real-Time Error Detection (RTD) Architecture and Its Use for Reliability and Post-Silicon Validation for F/F Based Memory Arrays. IEEE Trans. Emerg. Top. Comput. Yiannakis Sazeides, Arkady Bramnik, Ron Gabor, Ramon Canal
2022	A*	`conf`	AgilePkgC: An Agile System Idle State Architecture for Energy Proportional Datacenter Servers. MICRO Georgia Antoniou, Haris Volos, Davide B. Bartolini, Tom Rollet, Yiannakis Sazeides, Jawad Haj-Yahya
2022	J	`jnl`	AgilePkgC: An Agile System Idle State Architecture for Energy Proportional Datacenter Servers. CoRR Georgia Antoniou, Haris Volos, Davide B. Bartolini, Tom Rollet, Yiannakis Sazeides, Jawad Haj-Yahya
2022	A*	`conf`	AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications. MICRO Jawad Haj-Yahya, Haris Volos, Davide B. Bartolini, Georgia Antoniou, Jeremie S. Kim, Zhe Wang, Kleovoulos Kalaitzidis, Tom Rollet, Zhirui Chen, Ye Geng, Onur Mutlu, Yiannakis Sazeides
2022	J	`jnl`	AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications. CoRR Jawad Haj-Yahya, Haris Volos, Davide B. Bartolini, Georgia Antoniou, Jeremie S. Kim, Zhe Wang, Kleovoulos Kalaitzidis, Tom Rollet, Zhirui Chen, Ye Geng, Onur Mutlu, Yiannakis Sazeides
2022	A*	`conf`	IDLD: Instantaneous Detection of Leakage and Duplication of Identifiers used for Register Renaming. MICRO Yiannakis Sazeides, Alex Gerber, Ron Gabor, Arkady Bramnik, George Papadimitriou, Dimitris Gizopoulos, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Karyofyllis Patsidis
2022	—	`conf`	INTERPLAY: An Intelligent Model for Predicting Performance Degradation due to Multi-cache Way-disabling. DFT Panagiota Nikolaou, Yiannakis Sazeides, Maria K. Michael
2022	J	`jnl`	INTERPLAY: An Intelligent Model for Predicting Performance Degradation due to Multi-cache Way-disabling. CoRR Panagiota Nikolaou, Yiannakis Sazeides, Maria K. Michael
2022	J	`jnl`	On the Evaluation of the Total-Cost-of-Ownership Trade-Offs in Edge vs Cloud Deployments: A Wireless-Denial-of-Service Case Study. IEEE Trans. Sustain. Comput. Panagiota Nikolaou, Yiannakis Sazeides, Alejandro Lampropulos, Denis Guilhot, Andrea Bartoli, George Papadimitriou, Athanasios Chatzidimitriou, Dimitris Gizopoulos, Konstantinos Tovletoglou, Lev Mukhanov, Georgios Karakonstantis
2021	J	`jnl`	Harnessing CPU Electromagnetic Emanations for Resonance-Induced Voltage-Noise Characterization. IEEE Trans. Computers Zacharias Hadjilambrou, Shidhartha Das, Marco A. Antoniades, Yiannakis Sazeides
2021	J	`jnl`	I-DVFS: Instantaneous Frequency Switch During Dynamic Voltage and Frequency Scaling. IEEE Micro Alex Gendler, Ernest Knoll, Yiannakis Sazeides
2021	A	`conf`	SRAM Arrays with Built-in Parity Computation for Real-Time Error Detection in Cache Tag Arrays. DATE Ramon Canal, Yiannakis Sazeides, Arkady Bramnik
2020	—	`conf`	2D Error Correction for F/F based Arrays using In-Situ Real-Time Error Detection (RTD). DFT Yiannakis Sazeides, Arkady Bramnik, Ron Gabor, Chrysostomos Nicopoulos, Ramon Canal, Dimitris Konstantinou, Giorgos Dimitrakopoulos
2020	B	`conf`	Identification of an Entire Workload's CPU-Vmin from the n-First Seconds of its Execution Based on Performance Counters. ISPASS Panagiota Nikolaou, Yiannakis Sazeides
2020	B	`conf`	Performance Characterization of Simultaneous Multi-Threading and Index Partitioning for an Online Document Search Application. ISPASS Georgia Antoniou, Zacharias Hadjilambrou, Yiannakis Sazeides
2019	J	`jnl`	Comprehensive Characterization of an Open Source Document Search Engine. ACM Trans. Archit. Code Optim. Zacharias Hadjilambrou, Marios Kleanthous, Georgia Antoniou, Antoni Portero, Yiannakis Sazeides
2019	A	`conf`	Error-Shielded Register Renaming Sub-system for a Dynamically Scheduled Out-of-Order Core. DATE Ron Gabor, Yiannakis Sazeides, Arkady Bramnik, Alexandros Andreou, Chrysostomos Nicopoulos, Karyofyllis Patsidis, Dimitris Konstantinou, Giorgos Dimitrakopoulos
2019	B	`conf`	GeST: An Automatic Framework For Generating CPU Stress-Tests. ISPASS Zacharias Hadjilambrou, Shidhartha Das, Paul N. Whatmough, David M. Bull, Yiannakis Sazeides
2018	A	`conf`	An energy-efficient and error-resilient server ecosystem exceeding conservative scaling limits. DATE Georgios Karakonstantis, Konstantinos Tovletoglou, Lev Mukhanov, Hans Vandierendonck, Dimitrios S. Nikolopoulos, Peter Lawthers, Panos K. Koutsovasilis, Manolis Maroudas, Christos D. Antonopoulos, Christos Kalogirou, Nikolaos Bellas, Spyros Lalis, Srikumar Venugopal, Arnau Prat-Pérez, Alejandro Lampropulos, Marios Kleanthous, Andreas Diavastos, Zacharias Hadjilambrou, Panagiota Nikolaou, Yiannakis Sazeides, Pedro Trancoso, George Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, Dimitris Gizopoulos, Shidhartha Das
2018	A*	`conf`	Don't Correct the Tags in a Cache, Just Check Their Hamming Distance from the Lookup Tag. HPCA Alex Gendler, Arkady Bramnik, Ariel Szapiro, Yiannakis Sazeides
2018	—	`conf`	Fast Estimations of Failure Probability Over Long Time Spans. NANOARCH Michail Noltsis, Panayiotis Englezakis, Eleni Maragkoudaki, Chrysostomos Nicopoulos, Dimitrios Rodopoulos, Francky Catthoor, Yiannakis Sazeides, Davide Zoni, Dimitrios Soudris
2018	A*	`conf`	Leveraging CPU Electromagnetic Emanations for Voltage Noise Characterization. MICRO Zacharias Hadjilambrou, Shidhartha Das, Marco A. Antoniades, Yiannakis Sazeides
2018	—	`conf`	Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs. DSN Workshops Konstantinos Tovletoglou, Lev Mukhanov, Georgios Karakonstantis, Athanasios Chatzidimitriou, George Papadimitriou, Manolis Kaliorakis, Dimitris Gizopoulos, Zacharias Hadjilambrou, Yiannakis Sazeides, Alejandro Lampropulos, Shidhartha Das, Phong Vo
2018	J	`jnl`	Sensing CPU Voltage Noise Through Electromagnetic Emanations. IEEE Comput. Archit. Lett. Zacharias Hadjilambrou, Shidhartha Das, Marco A. Antoniades, Yiannakis Sazeides
2018	C	`conf`	To Detect or to Correct? IOLTS Arkady Bramnik, Yiannakis Sazeides
2017	J	`jnl`	A Methodology for Oracle Selection of Monitors and Knobs for Configuring an HPC System running a Flood Management Application. CoRR Panagiota Nikolaou, Yiannakis Sazeides, Antoni Portero, Radim Vavrík, Vít Vondrák
2017	J	`jnl`	BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers. J. Parallel Distributed Comput. Davide Zoni, Andrea Canidio, William Fornaciari, Panayiotis Englezakis, Chrysostomos Nicopoulos, Yiannakis Sazeides
2017	J	`jnl`	Error-Resilient Server Ecosystems for Edge and Cloud Datacenters. Computer Georgios Karakonstantis, Dimitrios S. Nikolopoulos, Dimitris Gizopoulos, Pedro Trancoso, Yiannakis Sazeides, Christos D. Antonopoulos, Srikumar Venugopal, Shidhartha Das
2017	A	`conf`	HARPA: Tackling physically induced performance variability. DATE Nikolaos Zompakis, Michail Noltsis, Lorena Ndreu, Zacharias Hadjilambrou, Panayiotis Englezakis, Panagiota Nikolaou, Antoni Portero, Simone Libutti, Giuseppe Massari, Federico Sassi, Alessandro Bacchini, Chrysostomos Nicopoulos, Yiannakis Sazeides, Radim Vavrík, Martin Golasowski, Jiri Sevcík, Vít Vondrák, Francky Catthoor, William Fornaciari, Dimitrios Soudris
2016	J	`jnl`	An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures. ACM Trans. Archit. Code Optim. Kypros Chrysanthou, Panayiotis Englezakis, Andreas Prodromou, Andreas Panteli, Chrysostomos Nicopoulos, Yiannakis Sazeides, Giorgos Dimitrakopoulos
2016	—	`conf`	Approximating Standard Cell Delay Distributions by Reformulating the Most Probable Failure Point. ERMAVSS@DATE Dimitrios Rodopoulos, Philippe Roussel, Francky Catthoor, Yiannakis Sazeides, Dimitrios Soudris
2016	A	`conf`	Probabilistic WCET estimation in presence of hardware for mitigating the impact of permanent faults. DATE Damien Hardy, Isabelle Puaut, Yiannakis Sazeides
2016	J	`jnl`	Toward Multi-Layer Holistic Evaluation of System Designs. IEEE Comput. Archit. Lett. Marios Kleanthous, Yiannakis Sazeides, Emre Özer, Chrysostomos Nicopoulos, Panagiota Nikolaou, Zacharias Hadjilambrou
2015	—	`conf`	HARPA: Solutions for dependable performance under physically induced performance variability. SAMOS Dimitrios Rodopoulos, Simone Corbetta, Giuseppe Massari, Simone Libutti, Francky Catthoor, Yiannakis Sazeides, Chrysostomos Nicopoulos, Antoni Portero, Etienne Cappe, Radim Vavrík, Vít Vondrák, Dimitrios Soudris, Federico Sassi, Agnes Fritsch, William Fornaciari
2015	A*	`conf`	Modeling the implications of DRAM failures and protection techniques on datacenter TCO. MICRO Panagiota Nikolaou, Yiannakis Sazeides, Lorena Ndreu, Marios Kleanthous
2013	B	`conf`	An analytical framework for estimating TCO and exploring data center design space. ISPASS Damien Hardy, Marios Kleanthous, Isidoros Sideris, Ali G. Saidi, Emre Ozer, Yiannakis Sazeides
2013	A*	`conf`	Implicit-storing and redundant-encoding-of-attribute information in error-correction-codes. MICRO Yiannakis Sazeides, Emre Özer, Danny Kershaw, Panagiota Nikolaou, Marios Kleanthous, Jaume Abella
2013	A	`conf`	Memory array protection: check on read or check on write? DATE Panagiota Nikolaou, Yiannakis Sazeides, Lorena Ndreu, Emre Özer, Sachin Idgunji
2013	J	`jnl`	Modeling the impact of permanent faults in caches. ACM Trans. Archit. Code Optim. Daniel Sánchez, Yiannakis Sazeides, Juan M. Cebrian, José M. García, Juan L. Aragón
2012	A*	`conf`	NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures. MICRO Andreas Prodromou, Andreas Panteli, Chrysostomos Nicopoulos, Yiannakis Sazeides
2012	J	`jnl`	Optimizing Data-Center TCO with Scale-Out Processors. IEEE Micro Boris Grot, Damien Hardy, Pejman Lotfi-Kamran, Babak Falsafi, Chrysostomos Nicopoulos, Yiannakis Sazeides
2012	A*	`conf`	The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults. MICRO Damien Hardy, Isidoros Sideris, Nikolas Ladas, Yiannakis Sazeides
2012	C	`conf`	Thermal characterization of cloud workloads on a power-efficient server-on-chip. ICCD Dragomir Milojevic, Sachin Idgunji, Djordje Jevdjic, Emre Ozer, Pejman Lotfi-Kamran, Andreas Panteli, Andreas Prodromou, Chrysostomos Nicopoulos, Damien Hardy, Babak Falsafi, Yiannakis Sazeides
2011	C	`conf`	An analytical model for the calculation of the Expected Miss Ratio in faulty caches. IOLTS Daniel Sánchez, Yiannakis Sazeides, Juan L. Aragón, José M. García
2011	J	`jnl`	CATCH: A mechanism for dynamically detecting cache-content-duplication in instruction caches. ACM Trans. Archit. Code Optim. Marios Kleanthous, Yiannakis Sazeides
2011	A	`conf`	Eliminating energy of same-content-cell-columns of on-chip SRAM arrays. ISLPED Bushra Ahsan, Lorena Ndreu, Isidoros Sideris, Yiannakis Sazeides, Sachin Idgunji, Emre Özer
2011	J	`jnl`	Improving Branch Prediction by Considering Affectors and Affectees Correlations. Trans. High Perform. Embed. Archit. Compil. Yiannakis Sazeides, Andreas Moustakas, Kypros Constantinides, Marios Kleanthous
2010	—	`conf`	Extrinsic and Intrinsic Text Cloning. ISCA Workshops Marios Kleanthous, Yiannakis Sazeides, Marios D. Dikaiakos
2010	B	`conf`	Performance-effective operation below Vcc-min. ISPASS Nikolas Ladas, Yiannakis Sazeides, Veerle Desmet
2010	—	`conf`	Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses. Conf. Computing Frontiers Pierre Michaud, Yiannakis Sazeides, André Seznec
2008	A	`conf`	CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication and its Application to Instruction Caches. DATE Marios Kleanthous, Yiannakis Sazeides
2008	—	`conf`	The Significance of Affectors and Affectees Correlations for Branch Prediction. HiPEAC Yiannakis Sazeides, Andreas Moustakas, Kypros Constantinides, Marios Kleanthous
2007	J	`jnl`	A study of thread migration in temperature-constrained multicores. ACM Trans. Archit. Code Optim. Pierre Michaud, André Seznec, Damien Fetis, Yiannakis Sazeides, Theofanis Constantinou
2005	J	`jnl`	Performance implications of single thread migration on a chip multi-core. SIGARCH Comput. Archit. News Theofanis Constantinou, Yiannakis Sazeides, Pierre Michaud, Damien Fetis, André Seznec
2005	J	`jnl`	The Danger of Interval-Based Power Efficiency Metrics: When Worst Is Best. IEEE Comput. Archit. Lett. Yiannakis Sazeides, Rakesh Kumar, Dean M. Tullsen, Theofanis Constantinou
2003	J	`jnl`	Instruction-Isomorphism in Program Execution. J. Instr. Level Parallelism Yiannakis Sazeides
2003	A	`conf`	Selecting long atomic traces for high coverage. ICS Roni Rosner, Micha Moffie, Yiannakis Sazeides, Ronny Ronen
2002	A*	`conf`	Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor. ISCA André Seznec, Stephen Felix, Venkata Krishnan, Yiannakis Sazeides
2002	A*	`conf`	Modeling Value Speculation. HPCA Yiannakis Sazeides
2001	B	`conf`	How to compare the performance of two SMT microarchitectures. ISPASS Yiannakis Sazeides, Toni Juan
1999	J	`jnl`	Limits of Data Value Predictability. Int. J. Parallel Program. Yiannakis Sazeides, James E. Smith
1998	A*	`conf`	Modeling Program Predictability. ISCA Yiannakis Sazeides, James E. Smith
1997	A*	`conf`	The Predictability of Data Values. MICRO Yiannakis Sazeides, James E. Smith
1997	A*	`conf`	Trace Processors. MICRO Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, James E. Smith
1996	A*	`conf`	The Performance Potential of Data Dependence Speculation & Collapsing. MICRO Yiannakis Sazeides, Stamatis Vassiliadis, James E. Smith