Yi Shen

55 papers Journal 42Unranked 13
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 12-bit 200-MS/s SAR ADC With Capacitor-Reuse-Based Redundant Weighting Technique.
IEEE Trans. Circuits Syst. II Express Briefs
Angyang Li, Yi Shen, Anji Huang, Shubin Liu, Ruixue Ding, Zhangming Zhu
2026 J jnl
A 75× scalable analog front-end with continuous bandwidth/power reconfigurability for bio-potential signal acquisition.
Microelectron. J.
Jianna Xiang, Yuke Shen, Jiahe Li, Jun Xiao, Yi Shen, Libo Qian, Yinshui Xia, Shubin Liu, Ruixue Ding
2026 J jnl
A 97.7 dB-SNDR 1 MS/s power/bandwidth scalable exponential-incremental noise-shaping pipeline ADC.
Microelectron. J.
Tao Chen, Yuke Shen, Bo Zhao, Deao Wu, Yi Shen, Libo Qian, Yinshui Xia, Shubin Liu, Ruixue Ding
2026 J jnl
Analysis and design of a sample-and-hold circuit with enhanced dual-noise-cancellation technique.
Microelectron. J.
Deao Wu, Yuke Shen, Tao Chen, Bo Zhao, Yi Shen, Shubin Liu
2026 J jnl
Design and analysis of a wideband low-fractional-spur, low-jitter Fractional-N digital PLL.
Microelectron. J.
Shanqi Zhan, Yanzhe Zhu, Chunlei Wang, Yihan Shen, Yi Shen, Ruixue Ding, Shubin Liu, Depeng Sun
2025 — conf
24.2 A 14b 1GS/s Single-Channel Pipelined ADC with A Parallel-Operation SAR Sub-Quantizer and A Dynamic-Deadzone Ring Amplifier.
ISSCC
Yue Cao, Yi Shen, Shubin Liu, Haolin Han, Hongzhi Liang, Li Dang, Dengquan Li, Ruixue Ding, Zhangming Zhu
2025 — conf
A 0.7-V 26.2-28.5 GHz Dual-Loop Double-Sampling PLL with Floating Capacitor OTA Based Gm-CP Achieving a 45.4-fsRMS Jitter.
CICC
Jun Chang, Hongzhi Liang, Yixiao Luo, Zeyu Peng, Zhe Li, Yi Shen, Shubin Liu, Zhangming Zhu
2025 J jnl
A 12-bit 1.5-GS/s Single-Channel Pipelined SAR ADC With a Pipelined Residue Amplification Stage.
IEEE J. Solid State Circuits
Yi Shen, Shubin Liu, Yue Cao, Haolin Han, Hongzhi Liang, Zhicheng Dong, Dengquan Li, Ruixue Ding, Zhangming Zhu
2025 — conf
A 13b 2GS/s Time-Domain Pipelined ADC with Split-CDAC Ping-Pong Residue Transfer and PVT-Robust Self-Tracked Time Amplifier.
CICC
Xin Zhao, Dengquan Li, Feida Wang, Depan Li, Yi Shen, Hongzhi Liang, Zhangming Zhu
2025 J jnl
A 2nd-order delta-sigma capacitance-to-digital converter with an embedded error-feedback exponential-incremental noise-shaping SAR quantizer.
Microelectron. J.
Bo Zhao, Yuke Shen, Tao Chen, Yi Shen, Shubin Liu, Ruixue Ding, Zhangming Zhu
2025 — conf
A 32GS/s 8b 16× Time-Interleaved Hybrid ADC with Self-Detection Offset Calibration, DLL-Based TLSB PVT Variation Calibration and VTC Gain Self-Tracking.
CICC
Hongzhi Liang, Jun Chang, Yixiao Luo, Zeyu Peng, Weimin Zhou, Li Dang, Yue Cao, Haolin Han, Yi Shen, Shubin Liu, Ruixue Ding, Zhangming Zhu
2025 J jnl
A 36.8-μW 66 nV/√Hz 85.7 dB-System-SNDR Reconfigurable Single-Channel ExG Acquisition System for Bio-Sensor Modules.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yuke Shen, Jiacheng Liu, Kui Wen, Yanbo Zhang, Yi Shen, Shubin Liu, Zhangming Zhu
2025 — conf
An 18-Bit 183.9dB-FoMS, DR MES/Calibration-Free Scalable Zoom ADC Using Fully Passive Coarse Modulator and Gain-Linearity-Enhanced FIA with Sub-1ppm-THD at Full Scale Input in 65-nm CMOS.
CICC
Yuke Shen, Shubin Liu, Deao Wu, Kui Wen, Yanbo Zhang, Yi Shen, Zhangming Zhu
2025 J jnl
An 8-bit 5-GS/s Single-Channel Hybrid ADC With a λ/4 Transmission Line Based Time Quantizer.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hongzhi Liang, Yi Shen, Jun Chang, Shubin Liu, Ruixue Ding, Zhangming Zhu
2025 J jnl
Power-efficient SAR ADC with noise-reduction scheme based on kT/C noise cancellation and adaptive tracking averaging.
Microelectron. J.
Anji Huang, Gefeng Zeng, Yi Shen, Angyang Li, Libo Qian, Qing Zou, Zheng Qiu, Min Wang, Shubin Liu, Ruixue Ding, Yinshui Xia, Zhangming Zhu
2025 J jnl
Rapid digital background calibration of bit weights in pipelined SAR ADC based on multi-PN injection.
Microelectron. J.
Le Chen, Yi Shen, Ruixue Ding, Shubin Liu, Haolin Han
2024 J jnl
A 14b 180MS/s Pipeline-SAR ADC With Adaptive-Region-Selection Technique and Gain Error Calibration.
IEEE Trans. Circuits Syst. II Express Briefs
Junyan Hao, Yi Shen, Jin Zhang, Yanbo Zhang, Shubin Liu, Zhangming Zhu
2024 J jnl
A 182.9-dB FoM 108.2-dB SFDR Power/Bandwidth Configurable Fully Dynamic Switched-Capacitor Zoom ADC With Interstage Leakage Shaping.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yuke Shen, Shubin Liu, Kui Wen, Yanbo Zhang, Yi Shen, Ruixue Ding, Zhangming Zhu
2024 J jnl
A 4-GS/s 6-Bit Single-Channel TDC-Assisted Hybrid ADC Featuring Power Supply Variation Adaptation for Inter-Stage Gain Error.
IEEE Trans. Circuits Syst. II Express Briefs
Hongzhi Liang, Shubin Liu, Ruixue Ding, Yi Shen, Dengquan Li, Zhangming Zhu
2024 J jnl
A 68.5 dB-SNDR, 12.4-fJ/conv.-step, 100-MS/s pipelined-SAR ADC with PVT-enhanced circuitry.
Microelectron. J.
Haolin Han, Ruili Ren, Yi Shen, Ruixue Ding, Shubin Liu, Hongzhi Liang
2024 J jnl
A Background Timing Skew Calibration for Time-Interleaved ADCs Based on Frequency Fitness Genetic Algorithm.
IEEE Trans. Instrum. Meas.
Dengquan Li, Longsheng Wang, Yi Shen, Shubin Liu, Zhangming Zhu
2024 J jnl
A High Accuracy and Bandwidth Digital Background Calibration Technique for Timing Skew in TI-ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Li Dang, Shubin Liu, Ruixue Ding, Yi Shen, Zhangming Zhu
2024 J jnl
A PVT-robust Gm-R-based residue amplifier with folded positive feedback technique.
Microelectron. J.
Haolin Han, Jinwei Zhang, Ruili Ren, Yi Shen, Shubin Liu, Ruixue Ding
2024 J jnl
A Power-Efficient Clock Circuit and Output Serializing Technique Integrated in a 12-bit 10-GS/s ADC.
IEEE Trans. Circuits Syst. I Regul. Pap.
Haolin Han, Shubin Liu, Hongzhi Liang, Yi Shen, Jianyu Guo, Ruili Ren, Zhangming Zhu
2024 J jnl
A Wideband Input Buffer Based on Cascade Complementary Source Follower.
IEEE Trans. Very Large Scale Integr. Syst.
Dengquan Li, Tian Feng, Jiale Ding, Yi Shen, Shubin Liu, Zhangming Zhu
2024 J jnl
A wide load-range OTA using a digitally assisted compensating technique.
Sci. China Inf. Sci.
Haolin Han, Shubin Liu, Yi Shen, Hongzhi Liang, Yue Cao, Longjie Zhong, Zhangming Zhu
2024 J jnl
Power-efficient 12-bit 800 MS/s voltage-time hybrid domain ADC with split TDC in 28 nm CMOS.
Microelectron. J.
Yun Li, Yi Shen, Yue Cao, Mengtong Wu, Li Dang, Shubin Liu, Ruixue Ding, Zhangming Zhu
2023 — conf
A $142.8-\mu \text{W}$ 98.1dB-SNDR Power/Bandwidth Configurable Fully Dynamic Discrete-Time Zoom ADC with Interstage Leakage Shaping.
A-SSCC
Yuke Shen, Shubin Liu, Kui Wen, Yanbo Zhang, Yi Shen, Ruixue Ding, Zhangming Zhu
2023 — conf
A 12b 1.5GS/s Single-Channel Pipelined SAR ADC with a Pipelined Residue Amplification Stage.
CICC
Yi Shen, Shubin Liu, Yue Cao, Haolin Han, Hongzhi Liang, Zhicheng Dong, Dengquan Li, Ruixue Ding, Zhangming Zhu
2023 — conf
A 5GS/s 38.04dB SNDR Single-Channel TDC-Assisted Hybrid ADC with $\lambda/4$ Transmission Line Based Time Quantizer Achieving a PVT Robustness 416.6fs Time Step.
A-SSCC
Hongzhi Liang, Yi Shen, Jun Chang, Shubin Liu, Ruixue Ding, Zhangming Zhu
2023 J jnl
A 7-bit 3.8-GS/s 2-Way Time-Interleaved 4-bit/Cycle SAR ADC 16× Time-Domain Interpolation in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Dengquan Li, Xin Zhao, Yi Shen, Shubin Liu, Zhangming Zhu
2023 J jnl
A Power-Efficient 13-Tap FIR Filter and an IIR Filter Embedded in a 10-Bit SAR ADC.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xin Xin, Linxiao Shen, Xiyuan Tang, Yi Shen, Jueping Cai, Xingyuan Tong, Nan Sun
2023 J jnl
An 8-bit 1.5-GS/s Two-Step SAR ADC With Embedded Interstage Gain.
IEEE Trans. Very Large Scale Integr. Syst.
Yi Shen, Junyan Hao, Shubin Liu, Zeshuai An, Dengquan Li, Ruixue Ding, Zhangming Zhu
2023 J jnl
An 8-bit 1.5-GS/s Voltage-Time Hybrid Two-Step ADC With Cross-Coupled Linearized VTC.
IEEE Trans. Very Large Scale Integr. Syst.
Xin Zhao, Dengquan Li, Feida Wang, Yi Shen, Shubin Liu, Ruixue Ding, Zhangming Zhu
2023 J jnl
An Energy-Efficient SAR ADC With a Coarse-Fine Bypass Window Technique.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yi Shen, Jian Liu, Chenxi Han, Angyang Li, Shubin Liu, Ruixue Ding, Zhangming Zhu
2023 J jnl
An offset and gain error calibration method in high-precision SAR ADCs.
Microelectron. J.
Junyan Hao, Yi Shen, Angyang Li, Min Wang, Qing Zou, Zheng Qiu, Shubin Liu, Zhangming Zhu
2022 J jnl
A 10-bit 100-MS/s SAR ADC With Always-On Reference Ripple Cancellation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yi Shen, Xiyuan Tang, Xin Xin, Shubin Liu, Zhangming Zhu, Nan Sun
2022 J jnl
A Fast Convergence Second-Order Compensation for Timing Skew in Time-Interleaved ADCs.
IEEE Trans. Very Large Scale Integr. Syst.
Dengquan Li, Lei Zhao, Longsheng Wang, Yi Shen, Zhangming Zhu
2022 — conf
A Wideband High-linearity Input Buffer Based on Cascade Complementary Source Follower.
ICTA
Tian Feng, Dengquan Li, Jiale Ding, Shubin Liu, Yi Shen, Zhangming Zhu
2022 J jnl
A loop-unrolled assisted 9b 700 MS/s nonbinary 2b/cycle SAR ADC with time-based offset calibration.
Microelectron. J.
Yukai Huang, Jiale Ding, Dengquan Li, Xin Zhao, Shubin Liu, Yi Shen, Zhangming Zhu
2022 J jnl
Analysis and Design of a High-Bandwidth Front-End Sampler for Time-Interleaved ADCs.
Circuits Syst. Signal Process.
Jiale Ding, Yukai Huang, Dengquan Li, Shubin Liu, Yi Shen, Zhangming Zhu
2022 J jnl
Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xiyuan Tang, Jiaxin Liu, Yi Shen, Shaolan Li, Linxiao Shen, Arindam Sanyal, Kareem Ragab, Nan Sun
2020 — conf
A 10-Bit 100-MS/s SAR ADC with Always-on Reference Ripple Cancellation.
VLSI Circuits
Xiyuan Tang, Yi Shen, Xin Xin, Shubin Liu, Jueping Cai, Zhangming Zhu, Nan Sun
2020 J jnl
A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique.
IEEE J. Solid State Circuits
Yi Shen, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Xin Xin, Shubin Liu, Zhangming Zhu, Visvesh Sathe, Nan Sun
2020 J jnl
A 12-Bit 100-MS/s Pipelined-SAR ADC With PVT-Insensitive and Gain-Folding Dynamic Amplifier.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shubin Liu, Haolin Han, Yi Shen, Zhangming Zhu
2020 — conf
A Power-Efficient 13-Tap FIR filter and an IIR Filter Embedded in a 10-bit SAR ADC.
A-SSCC
Xin Xin, Linxiao Shen, Xiyuan Tang, Yi Shen, Jueping Cai, Nan Sun
2019 — conf
A 0.01mm
ISSCC
Linxiao Shen, Yi Shen, Xiyuan Tang, Chen-Kai Hsu, Wei Shi, Shaolan Li, Wenda Zhao, Abhishek Mukherjee, Nan Sun
2019 — conf
A 10b 120MS/s SAR ADC with Reference Ripple Cancellation Technique.
CICC
Xiyuan Tang, Yi Shen, Linxiao Shen, Wenda Zhao, Zhangming Zhu, Visvesh Sathe, Nan Sun
2019 J jnl
A Two-Step ADC With a Continuous-Time SAR-Based First Stage.
IEEE J. Solid State Circuits
Linxiao Shen, Nan Sun, Yi Shen, Zhelu Li, Wei Shi, Xiyuan Tang, Shaolan Li, Wenda Zhao, Mantian Zhang, Zhangming Zhu
2018 J jnl
A Reconfigurable 10-to-12-b 80-to-20-MS/s Bandwidth Scalable SAR ADC.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yi Shen, Zhangming Zhu, Shubin Liu, Yintang Yang
2018 J jnl
Low-Power Single-Ended SAR ADC Using Symmetrical DAC Switching for Image Sensors With Passive CDS and PGA Technique.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jingyu Wang, Shubin Liu, Yi Shen, Zhangming Zhu
2016 J jnl
A 12-Bit 10 MS/s SAR ADC With High Linearity and Energy-Efficient Switching.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shubin Liu, Yi Shen, Zhangming Zhu
2016 J jnl
A 12-bit 50MS/s zero-crossing-based two-stage pipelined SAR ADC in 0.18 µm CMOS.
Microelectron. J.
Yi Shen, Shubin Liu, Zhangming Zhu
2016 J jnl
Analysis and optimization of the two-stage pipelined SAR ADCs.
Microelectron. J.
Yi Shen, Zhangming Zhu
2014 J jnl
A 2.67 fJ/c.-s. 27.8 kS/s 0.35 V 10-bit successive approximation register analogue-to-digital converter in 65 nm complementary metal oxide semiconductor.
IET Circuits Devices Syst.
Zhangming Zhu, Zheng Qiu, Yi Shen, Yintang Yang