Yi-Yu Liu

30 papers A 12C 1Journal 14Unranked 3
YearRankTypeTitle / Venue / Authors
2026 J jnl
Clustered-based Multi-pin Substrate Routing Optimization for Fine-Pitch Ball Grid Array.
ACM Trans. Design Autom. Electr. Syst.
Ming-Yen Chuang, Yu-En Lin, Yi-Yu Liu
2026 J jnl
Optimization Heuristics for Grid-Based Integer Linear Programming Package Substrate Router.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chen-Yu Hsieh, Yu-En Lin, Yi-Yu Liu
2025 A conf
(Invited Paper) Overview of 2025 CAD Contest at ICCAD.
ICCAD
Chung-Kuan Cheng, Shao-Yun Fang, Yi-Yu Liu, Tsun-Ming Tseng
2025 — conf
Paired-Spacing-Constrained Package Routing with Net Ordering Optimization.
ASP-DAC
Yi-Sian Ciou, Ying-Jie Jiang, Yi-Yu Liu, Shao-Yun Fang, Wen-Hao Liu
2025 A conf
Refinement Strategies for Any-Angle Package Routing with I/O Alignment Consideration.
ICCAD
Yu-En Lin, Shao-Yun Fang, Yi-Yu Liu
2025 A conf
Wire-Bonding Finger Placement for FBGA Substrate Layout Design with Finger Orientation Consideration.
DATE
Yu-En Lin, Yi-Yu Liu
2024 J jnl
A Cost-Driven Chip Partitioning Method for Heterogeneous 3D Integration.
ACM Trans. Design Autom. Electr. Syst.
Cheng-Hsien Lin, Kuan-Ting Chen, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang
2024 A conf
Overview of 2024 CAD contest at ICCAD.
ICCAD
Shao-Yun Fang, Yi-Yu Liu, Chung-Kuan Cheng, Tsun-Ming Tseng
2023 J jnl
Enhanced and Efficient Guiding Template Design for Lamellar DSA With Graph Monomorphism.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yi-Sian Ciou, An-Jie Shih, Shao-Yun Fang, Yi-Yu Liu
2023 J jnl
ILP-based Substrate Routing with Mismatched Via Dimension Consideration for Wire-bonding FBGA Package Design.
ACM Trans. Design Autom. Electr. Syst.
Jun-Sheng Wu, Chi-An Pan, Yi-Yu Liu
2021 J jnl
TSE: Two-Step Elimination for MLC STT-RAM Last-Level Cache.
IEEE Trans. Computers
Jen-Wei Hsieh, Yi-Yu Liu, Hung-Tse Lee, Tai Chang
2020 A conf
Guiding Template Design for Lamellar DSA with Multiple Patterning and Self-Aligned Via Process.
ICCAD
An-Jie Shih, Shao-Yun Fang, Yi-Yu Liu
2017 J jnl
A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability Enhancements.
IEEE Trans. Very Large Scale Integr. Syst.
Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang
2016 A conf
A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements.
DATE
Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang
2014 J jnl
Buffer Design and Assignment for Structured ASIC.
J. Inf. Sci. Eng.
Po-Yang Hsu, Yi-Yu Liu
2014 J jnl
Hybrid LUT and SOP Reconfigurable Architecture.
J. Inf. Sci. Eng.
Po-Yang Hsu, Yung-Chih Chen, Yi-Yu Liu
2013 A conf
Dual-addressing memory architecture for two-dimensional memory access patterns.
DATE
Yen-Hao Chen, Yi-Yu Liu
2013 J jnl
Memory management for dual-addressing memory architecture.
IEICE Electron. Express
Ting-Wei Hung, Yen-Hao Chen, Yi-Yu Liu
2013 J jnl
Routability optimization for crossbar-switch structured ASIC design.
ACM Trans. Design Autom. Electr. Syst.
Mei-Hsiang Tsai, Po-Yang Hsu, Hung-Yi Li, Yi-Huang Hung, Yi-Yu Liu
2010 C conf
Identifying Prostate Cancer-Related Networks from Microarray Data Based on Genotype-Phenotype Networks Using Markov Blanket Search.
BIBE
Hsiang-Yuan Yeh, Yi-Yu Liu, Cheng-Yu Yeh, Von-Wun Soo
2010 J jnl
Performance-Driven Dual-Rail Routing Architecture for Structured ASIC Design Style.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Fu-Wei Chen, Yi-Yu Liu
2009 — conf
Buffer design and optimization for lut-based structured ASIC design styles.
ACM Great Lakes Symposium on VLSI
Po-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu
2009 A conf
Performance-driven dual-rail insertion for chip-level pre-fabricated design.
DATE
Fu-Wei Chen, Yi-Yu Liu
2008 A conf
Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture.
DATE
Fu-Wei Chen, Yi-Yu Liu
2007 J jnl
Crosstalk-Aware Domino-Logic Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yi-Yu Liu, TingTing Hwang
2006 J jnl
Crosstalk minimization in logic synthesis for PLAs.
ACM Trans. Design Autom. Electr. Syst.
Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang
2006 A conf
Crosstalk-aware domino logic synthesis.
DATE
Yi-Yu Liu, TingTing Hwang
2004 A conf
Crosstalk Minimization in Logic Synthesis for PLA.
DATE
Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang
2001 — conf
A construction of minimal delay Steiner tree using two-pole delay model.
ASP-DAC
LiYi Lin, Yi-Yu Liu, TingTing Hwang
2001 A conf
Binary decision diagram with minimum expected path length.
DATE
Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang, C. L. Liu