Yi-Wei Lin - RankMe

31 papers A* 1A 1B 1C 6Misc 1Journal 11Unranked 10

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Programmable CMOS DEP Chip for Cell Manipulation. IEEE Trans. Biomed. Circuits Syst. Wen-Yue Lin, Lin-Hung Lai, Yi-Wei Lin, Chen-Yi Lee
2024	C	`conf`	A 2.56-µs Dynamic Range, 31.25-ps Resolution 2-D Vernier Digital-to-Time Converter (DTC) for Cell-Monitoring. ISCAS Heng-Yu Liu, Lin-Hung Lai, Wen-Yue Lin, Yu-Wei Lu, Yi-Wei Lin, Chen-Yi Lee
2024	C	`conf`	A Programmable CMOS Dielectrophoresis Array Chip with 128 × 128 Electrodes for Cell Manipulation. ISCAS Wen-Yue Lin, Lin-Hung Lai, Yi-Wei Lin, Chen-Yi Lee
2024	—	`conf`	Optimal Growth Conditions for Human Endometrial Stromal Cells in a Bidirectional OoC with Porous Membrane. IEEE SENSORS Pin-Yao Lee, Yi-Wen Wang, Ying-Fang Chang, Ming-Jyh Chang, Yi-Wei Lin, Hong-Yuan Huang, Da-Jeng Yao
2024	J	`jnl`	Satellite hyperspectral imagery reveals scale dependence of functional diversity patterns in a Qinghai-Tibetan alpine meadow. Int. J. Appl. Earth Obs. Geoinformation Yi-Wei Zhang, Yanpei Guo, Yuhao Feng, Zhenhua Zhang, Rong Tang, Yun-Hao Bai, Hong-Tu Zhang, Yi-Wei Lin, Jiangling Zhu, Tiejun Wang, Zhiyao Tang
2023	J	`jnl`	Effects of voice assistant creation using different learning approaches on performance of computational thinking. Comput. Educ. Ting-Chia Hsu, Ching Chang, Yi-Wei Lin
2022	—	`conf`	Understanding Intention to Use Netflix in Taiwan: Integrating Perceived Value into the Technology Acceptance Model. ICISE Chih Ming Tsai, Yi-Wei Lin
2022	J	`jnl`	Using robot-based practices to develop an activity that incorporated the 6E model to improve elementary school students' learning performances. Interact. Learn. Environ. Hsien-Sheng Hsiao, Yi-Wei Lin, Kuen-Yi Lin, Chien-Yu Lin, Jheng-Han Chen, Jyun-Chen Chen
2017	J	`jnl`	A Sierpinski Space-Filling Clock Tree Using Multiply-by-3 Fractal-Coupled Ring Oscillators. IEEE J. Solid State Circuits Yi-Wei Lin, Shawn S. H. Hsu
2014	Misc	`conf`	Mining mobile application sequential patterns for usage prediction. GrC Eric Hsueh-Chan Lu, Yi-Wei Lin, Jing-Bin Ciou
2013	C	`conf`	A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist. ISCAS Chi-Shin Chang, Hao-I Yang, Wei-Nan Liao, Yi-Wei Lin, Nan-Chun Lien, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Ming-Hsien Tu, Huan-Shun Huang, Yong-Jyun Hu, Paul-Sen Kan, Cheng-Yo Cheng, Wei-Chang Wang, Jian-Hao Wang, Kuen-Di Lee, Chia-Cheng Chen, Wei-Chiang Shih
2013	J	`jnl`	Quality improvement of optical lenses using innovative runner design. Int. J. Manuf. Res. Kuo-Ming Tsai, Yi-Wei Lin
2012	A	`conf`	A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist. ISLPED Yi-Wei Lin, Hao-I Yang, Geng-Cing Lin, Chi-Shin Chang, Ching-Te Chuang, Wei Hwang, Chia-Cheng Chen, Willis Shih, Huan-Shun Huang
2012	—	`conf`	A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assist. SoCC Yung-Wei Lin, Hao-I Yang, Mao-Chih Hsia, Yi-Wei Lin, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu
2012	—	`conf`	An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array. VLSI-DAT Yi-Wei Lin, Ming-Chien Tsai, Hao-I Yang, Geng-Cing Lin, Shao-Cheng Wang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih
2012	C	`conf`	An all-digital bit transistor characterization scheme for CMOS 6T SRAM array. ISCAS Geng-Cing Lin, Shao-Cheng Wang, Yi-Wei Lin, Ming-Chien Tsai, Ching-Te Chuang, Shyh-Jye Jou, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, Jyun-Kai Chu
2012	J	`jnl`	Application of fuzzy-based Taguchi method to the optimization of extrusion of magnesium alloy bicycle carriers. J. Intell. Manuf. Su-Hai Hsiang, Yi-Wei Lin, Jhong-Wei Lai
2012	—	`conf`	Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM. APCCAS Shao-Cheng Wang, Geng-Cing Lin, Yi-Wei Lin, Ming-Chien Tsai, Yi-Wei Chiu, Shyh-Jye Jou, Ching-Te Chuang, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, Jyun-Kai Chu
2012	—	`conf`	Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array. VLSI-DAT Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee, Shyh-Jye Jou, Ching-Te Chuang, Wei Hwang
2012	C	`conf`	High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder. ISCAS Hao-I Yang, Yi-Wei Lin, Mao-Chih Hsia, Geng-Cing Lin, Chi-Shin Chang, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu
2012	J	`jnl`	MoNetFamily: a web server to infer homologous modules and module-module interaction networks in vertebrates. Nucleic Acids Res. Chun-Yu Lin, Yi-Wei Lin, Shang-Wen Yu, Yu-Shu Lo, Jinn-Moon Yang
2011	—	`conf`	A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control. SoCC Hao-I Yang, Shih-Chi Yang, Mao-Chih Hsia, Yung-Wei Lin, Yi-Wei Lin, Chien-Hen Chen, Chi-Shin Chang, Geng-Cing Lin, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu
2011	J	`jnl`	On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly
2010	J	`jnl`	Layout Generator for Transistor-Level High-Density Regular Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly
2010	—	`conf`	Performance study of VeSFET-based, high-density regular circuits. ISPD Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly
2009	—	`conf`	Transistor-level layout of high-density regular circuits. ISPD Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly
2008	C	`conf`	Is there always performance overhead for regular fabric? ICCD Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly, Andrzej Pfitzner, Dominik Kasprowicz
2007	A*	`conf`	OPC-Free and Minimally Irregular IC Design Style. DAC Wojciech Maly, Yi-Wei Lin, Malgorzata Marek-Sadowska
2006	J	`jnl`	REDUP: a packet loss recovery scheme for real-time audio streaming over wireless IP networks. J. Syst. Softw. Chung-Ming Huang, Tz-Heng Hsu, Yi-Wei Lin
2004	—	`conf`	An efficient approach for hierarchical submodule extraction. ISCAS (5) Yi-Wei Lin, Jing-Yang Jou
2003	B	`conf`	An Adaptive Control Scheme for Real-Time Media Streaming over Wireless Networks. AINA Chung-Ming Huang, Yuan-Tse Yu, Yi-Wei Lin