Yi-Min Jiang

21 papers A* 2A 6Journal 7Unranked 6
YearRankTypeTitle / Venue / Authors
2022 — conf
Congestion and Timing Aware Macro Placement Using Machine Learning Predictions from Different Data Sources: Cross-design Model Applicability and the Discerning Ensemble.
ISPD
Xiang Gao, Yi-Min Jiang, Lixin Shao, Pedja Raspopovic, Menno E. Verbeek, Manish Sharma, Vineet Rashingkar, Amit Jalota
2014 J jnl
A method of batching conflict routings in shuffle-exchange networks.
Theor. Comput. Sci.
Yi-Hao Zhang, Yue-hong Shen, Min Dong, Yi-Min Jiang
2008 J jnl
Simultaneous Sleep Transistor Insertion and Power Network Synthesis for Industrial Power Gating Designs.
J. Comput.
Kaijian Shi, Zhian Lin, Yi-Min Jiang, Lin Yuan
2007 — conf
A Power Network Synthesis Method for Industrial Power Gating Designs.
ISQED
Kaijian Shi, Zhian Lin, Yi-Min Jiang
2003 J jnl
Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng
2001 A conf
Delay testing considering crosstalk-induced effects.
ITC
Angela Krstic, Jing-Jia Liou, Yi-Min Jiang, Kwang-Ting Cheng
2001 — conf
HRM - A Hierarchical Simulator for Full-Chip Power Network Reliability Analysis.
ISQED
Yi-Min Jiang, Han Young Koh, Kwang-Ting Cheng
2001 J jnl
Pattern generation for delay testing and dynamic timing analysisconsidering power-supply noise effects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng
2001 J jnl
Vector generation for power supply noise estimation and verification of deep submicron designs.
IEEE Trans. Very Large Scale Integr. Syst.
Yi-Min Jiang, Kwang-Ting Cheng
2000 — conf
Dynamic Timing Analysis Considering Power Supply Noise Effects.
ISQED
Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng
2000 J jnl
Estimation for maximum instantaneous current through supply lines for CMOS circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng
2000 A conf
Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects.
ICCAD
Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng
1999 A* conf
Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices.
DAC
Yi-Min Jiang, Kwang-Ting Cheng
1999 A conf
Delay testing considering power supply noise effects.
ITC
Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng
1999 A conf
VIP - an input pattern generator for indentifying critical voltage drop for deep sub-micron designs.
ISLPED
Yi-Min Jiang, Tak K. Young, Kwang-Ting Cheng
1998 — conf
A Hybrid Power Model for RTL Power Estimation.
ASP-DAC
Yi-Min Jiang, Shi-Yu Huang, Kwang-Ting Cheng, Deborah C. Wang, ChingYen Ho
1998 A conf
Estimation of maximum power supply noise for deep sub-micron designs.
ISLPED
Yi-Min Jiang, Kwang-Ting Cheng, An-Chang Deng
1998 A conf
Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits.
DATE
Yi-Min Jiang, Kwang-Ting Cheng
1997 A* conf
Post-Layout Logic Restructuring for Performance Optimization.
DAC
Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng, Malgorzata Marek-Sadowska
1994 J jnl
Performance-driven interconnection optimization for microarchitecture synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Youn-Long Lin
1992 — conf
Performance-driven interconnection optimization for microarchitecture synthesis.
EURO-DAC
Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Yaun-Long Lin