Yi-Lin Chuang

14 papers A* 3A 6Journal 4Unranked 1
YearRankTypeTitle / Venue / Authors
2025 A* conf
Power-Grid Structure Exploration with Unified Sequence-based Learning Framework.
DAC
Yi-Lin Chuang, Hao-Wei Chan, Chih-Yun Yen, Shih-An Hsieh, Ching-Feng Chen, Sheng-Te Lai
2020 A* conf
Exploring the Design Space of User-System Communication for Smart-home Routine Assistants.
CHI
Yi-Shyuan Chiang, Ruei-Che Chang, Yi-Lin Chuang, Shih-Ya Chou, Hao-Ping Lee, I-Ju Lin, Jian-Hua Jiang Chen, Yung-Ju Chang
2014 J jnl
Pulsed-Latch Utilization for Clock-Tree Power Optimization.
IEEE Trans. Very Large Scale Integr. Syst.
Hong-Ting Lin, Yi-Lin Chuang, Zong-Han Yang, Tsung-Yi Ho
2012 A conf
Statistical thermal modeling and optimization considering leakage power variations.
DATE
Da-Cheng Juan, Yi-Lin Chuang, Diana Marculescu, Yao-Wen Chang
2011 A conf
PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs.
ICCAD
Yi-Lin Chuang, Hong-Ting Lin, Tsung-Yi Ho, Yao-Wen Chang, Diana Marculescu
2011 J jnl
Pulsed-Latch Aware Placement for Timing-Integrity Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang
2011 A conf
Pulsed-latch-based clock tree migration for dynamic power reduction.
ISLPED
Hong-Ting Lin, Yi-Lin Chuang, Tsung-Yi Ho
2011 J jnl
Voltage-Drop Aware Analytical Placement by Global Power Spreading for Mixed-Size Circuit Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yi-Lin Chuang, Po-Wei Lee, Yao-Wen Chang
2010 A conf
Design-hierarchy aware mixed-size placement for routability optimization.
ICCAD
Yi-Lin Chuang, Gi-Joon Nam, Charles J. Alpert, Yao-Wen Chang, Jarrod A. Roy, Natarajan Viswanathan
2010 A* conf
Pulsed-latch aware placement for timing-integrity optimization.
DAC
Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang
2009 A conf
Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs.
ICCAD
Yi-Lin Chuang, Po-Wei Lee, Yao-Wen Chang
2008 A conf
Constraint graph-based macro placement for modern mixed-size circuit designs.
ICCAD
Hsin-Chen Chen, Yi-Lin Chuang, Yao-Wen Chang, Yung-Chung Chang
2008 J jnl
Effective Wire Models for X-Architecture Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang
2007 — conf
X-architecture placement based on effective wire models.
ISPD
Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang