Yi-Jung Chen

22 papers A* 1A 5C 1Misc 3Journal 6Unranked 6
YearRankTypeTitle / Venue / Authors
2025 A conf
Filter-Based Adaptive Model Pruning for Efficient Incremental Learning on Edge Devices.
DATE
Jing-Jia Hung, Yi-Jung Chen, Hsiang-Yun Cheng, Hsu Kao, Chia-Lin Yang
2025 — conf
Image Recognition Based Precursor Detection System for Landslide Prevention.
SII
Yuhei Oguro, Yihsin Ho, Jie-Ru Chen, Yi-Jung Chen
2023 A* conf
Tensor Movement Orchestration in Multi-GPU Training Systems.
HPCA
Shao-Fu Lin, Yi-Jung Chen, Hsiang-Yun Cheng, Chia-Lin Yang
2022 — conf
PUMP: Profiling-free Unified Memory Prefetcher for Large DNN Model Support.
ASP-DAC
Chung-Hsiang Lin, Shao-Fu Lin, Yi-Jung Chen, En-Yu Jenp, Chia-Lin Yang
2020 Misc conf
Thermal-aware memory system synthesis for MPSoCs with 3D-stacked hybrid memories.
SAC
Chia-Yin Liu, Yi-Jung Chen, Masanori Hariyama
2018 — conf
Thermal-aware task and data co-allocation for multi-processor system-on-chips with 3D-stacked memories.
RACS
Chia-Yin Liu, Cheng-En Wu, Yi-Jung Chen
2017 J jnl
Exploiting Write Heterogeneity of Morphable MLC/SLC SSDs in Datacenters with Service-Level Objectives.
IEEE Trans. Computers
Che-Wei Chang, Geng-You Chen, Yi-Jung Chen, Chia-Wei Yeh, Pei Yin Eng, Ana Cheung, Chia-Lin Yang
2017 J jnl
Processors Allocation for MPSoCs With Single ISA Heterogeneous Multi-Core Architecture.
IEEE Access
Yi-Jung Chen, Wen-Wei Chang, Chia-Yin Liu, Cheng-En Wu, Bo-Yuan Chen, Ming-Ying Tsai
2015 J jnl
SECRET: A Selective Error Correction Framework for Refresh Energy Reduction in DRAMs.
ACM Trans. Archit. Code Optim.
Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang
2015 — conf
Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs.
RACS
Yi-Jung Chen, Chia-Lin Yang, Ping-Sheng Lin, Yi-Chang Lu
2014 A conf
Scenario-aware data placement and memory area allocation for Multi-Processor System-on-Chips with reconfigurable 3D-stacked SRAMs.
DATE
Meng-Ling Tsai, Yi-Jung Chen, Yi-Ting Chen, Ru-Hua Chang
2013 A conf
Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs.
ISLPED
Ping-Sheng Lin, Yi-Jung Chen, Chia-Lin Yang, Yi-Chang Lu
2012 A conf
Distributed memory interface synthesis for Network-on-Chips with 3D-stacked DRAMs.
ICCAD
Yi-Jung Chen, Chia-Lin Yang, Jian-Jia Chen
2012 C conf
SECRET: Selective error correction for refresh energy reduction in DRAMs.
ICCD
Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang
2011 J jnl
TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems.
IEEE Trans. Computers
Yi-Jung Chen, Chia-Lin Yang, Jaw-Wei Chi, Jian-Jia Chen
2010 A conf
PM-COSYN: PE and memory co-synthesis for MPSoCs.
DATE
Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang
2009 J jnl
An architectural co-synthesis algorithm for energy-aware Network-on-Chip design.
J. Syst. Archit.
Yi-Jung Chen, Chia-Lin Yang, Yen-Sheng Chang
2007 Misc conf
An architectural co-synthesis algorithm for energy-aware network-on-chip design.
SAC
Wei-Hsuan Hung, Yi-Jung Chen, Chia-Lin Yang, Yen-Sheng Chang, Alan P. Su
2007 Misc conf
Cache leakage control mechanism for hard real-time systems.
CASES
Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia Chen
2007 J jnl
Improved Modulo (2n+1) Multiplier for IDEA.
J. Inf. Sci. Eng.
Yi-Jung Chen, Dyi-Rong Duh, Yunghsiang Sam Han
2006 — conf
Branch Behavior Characterization for Multimedia Applications.
Asia-Pacific Computer Systems Architecture Conference
Chia-Lin Yang, Shun-Ying Wang, Yi-Jung Chen
2004 — conf
A New Modulo (2
Security and Management
Yi-Jung Chen, Dyi-Rong Duh, Yunghsiang S. Han