Yi-Hsiang Lai - RankMe

16 papers A* 2A 10Journal 4

Year	Rank	Type	Title / Venue / Authors
2026	A	`conf`	AdaServe: Accelerating Multi-SLO LLM Serving with SLO-Customized Speculative Decoding. EuroSys Zikun Li, Zhuofu Chen, Remi Delacourt, Gabriele Oliaro, Zeyu Wang, Qinghan Chen, Shuhuai Lin, April Yang, Zhihao Zhang, Zhuoming Chen, Yi-Hsiang Lai, Xinhao Cheng, Xupeng Miao, Zhihao Jia
2024	A	`conf`	Automated Deep Learning Optimization via DSL-Based Source Code Transformation. ISSTA Ruixin Wang, Minghai Lu, Cody Hao Yu, Yi-Hsiang Lai, Tianyi Zhang
2024	J	`jnl`	Automated Deep Learning Optimization via DSL-Based Source Code Transformation. CoRR Ruixin Wang, Minghai Lu, Cody Hao Yu, Yi-Hsiang Lai, Tianyi Zhang
2022	A*	`conf`	Accelerator design with decoupled hardware customizations: benefits and challenges: invited. DAC Debjit Pal, Yi-Hsiang Lai, Shaojie Xiang, Niansong Zhang, Hongzheng Chen, Jeremy Casas, Pasquale Cocchini, Zhenkun Yang, Jin Yang, Louis-Noël Pouchet, Zhiru Zhang
2022	A	`conf`	HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for Software-Defined FPGAs. FPGA Shaojie Xiang, Yi-Hsiang Lai, Yuan Zhou, Hongzheng Chen, Niansong Zhang, Debjit Pal, Zhiru Zhang
2021	J	`jnl`	Bring Your Own Codegen to Deep Learning Compiler. CoRR Zhi Chen, Cody Hao Yu, Trevor Morris, Jorn Tuyls, Yi-Hsiang Lai, Jared Roesch, Elliott Delaye, Vin Sharma, Yida Wang
2021	J	`jnl`	Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects. ACM Trans. Reconfigurable Technol. Syst. Yi-Hsiang Lai, Ecenur Ustun, Shaojie Xiang, Zhenman Fang, Hongbo Rong, Zhiru Zhang
2020	A	`conf`	SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs. ICCAD Yi-Hsiang Lai, Hongbo Rong, Size Zheng, Weihao Zhang, Xiuping Cui, Yunshan Jia, Jie Wang, Brendan Sullivan, Zhiru Zhang, Yun Liang, Youhui Zhang, Jason Cong, Nithin George, Jose Alvarez, Christopher J. Hughes, Pradeep Dubey
2019	A	`conf`	HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing. FPGA Yi-Hsiang Lai, Yuze Chi, Yuwei Hu, Jie Wang, Cody Hao Yu, Yuan Zhou, Jason Cong, Zhiru Zhang
2018	A	`conf`	Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs. FPGA Yuan Zhou, Udit Gupta, Steve Dai, Ritchie Zhao, Nitish Kumar Srivastava, Hanchen Jin, Joseph Featherston, Yi-Hsiang Lai, Gai Liu, Gustavo Angarita Velasquez, Wenping Wang, Zhiru Zhang
2016	A	`conf`	Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits. ICCAD Nian-Ze Lee, Hao-Yuan Kuo, Yi-Hsiang Lai, Jie-Hong R. Jiang
2016	J	`jnl`	Scalable Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yi-Hsiang Lai, Chi-Chuan Chuang, Jie-Hong R. Jiang
2015	A	`conf`	A General Framework for Efficient Performance Analysis of Acyclic Asynchronous Pipelines. ICCAD Yi-Hsiang Lai, Chi-Chuan Chuang, Jie-Hong R. Jiang
2015	A	`conf`	Asynchronous QDI Circuit Synthesis from Signal Transition Protocols. ICCAD Bo-Yuan Huang, Yi-Hsiang Lai, Jie-Hong Roland Jiang
2015	A	`conf`	SPOCK: Static Performance Analysis and Deadlock Verification for Efficient Asynchronous Circuit Synthesis. ICCAD Chun-Hong Shih, Yi-Hsiang Lai, Jie-Hong Roland Jiang
2014	A*	`conf`	Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits. DAC Chi-Chuan Chuang, Yi-Hsiang Lai, Jie-Hong R. Jiang