Yi-Chang Lu - RankMe

72 papers A* 2A 7B 2C 12Misc 3Journal 10Unranked 36

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Energy-Efficient Basecalling for ONT Long Reads on a Hybrid ASIC-GPU Platform. ISVLSI Cheng-You Tsai, Hung-Yu Tseng, Po-Yen Chang, Yi-Chang Lu
2024	—	`conf`	A Memory-Efficient Accelerator for 128-Parallel Sequence-to-Graph Alignment in Variant-Enriched Regions. BioCAS Zhe-Wei Shen, Jheng-Syun Huang, Yi-Chang Lu
2024	A	`conf`	Deep Plug-and-play Nighttime Non-blind Deblurring with Saturated Pixel Handling Schemes. WACV Hung-Yu Shu, Yi-Hsien Lin, Yi-Chang Lu
2022	—	`conf`	A Hardware Accelerator for Long Sequence Alignment with the Bit-Vector Scoring Scheme and Divide-and-Conquer Traceback. BioCAS Chuan-Yu Chen, Shih-Hao Huang, Yi-Chang Lu
2022	—	`conf`	A Nucleotide-Position-Based Data Format for Fast Variant Calling and Its Hardware Analyzer Design. BioCAS Hao-Wei Liu, Zhe-Wei Shen, Yang-Ming Yeh, Yi-Chang Lu
2022	J	`jnl`	A Variation-Based Nighttime Image Dehazing Flow With a Physically Valid Illumination Estimator and a Luminance-Guided Coloring Model. IEEE Access Chih-Hsiang Yang, Yi-Hsien Lin, Yi-Chang Lu
2022	C	`conf`	An Alignment-Based Hardware Accelerator for Rapid Prediction of RNA Secondary Structures. ISCAS Shih-Shiuan Weng, Yang-Ming Yeh, Yu-Cheng Li, Yi-Chang Lu
2022	Misc	`conf`	CF-Net: Complementary Fusion Network for Rotation Invariant Point Cloud Completion. ICASSP Bo-Fan Chen, Yang-Ming Yeh, Yi-Chang Lu
2022	J	`jnl`	Low-Light Enhancement Using a Plug-and-Play Retinex Model With Shrinkage Mapping for Illumination Estimation. IEEE Trans. Image Process. Yi-Hsien Lin, Yi-Chang Lu
2022	J	`jnl`	MSRCall: a multi-scale deep neural network to basecall Oxford Nanopore sequences. Bioinform. Yang-Ming Yeh, Yi-Chang Lu
2022	A	`conf`	Shadow Removal Through Learning-Based Region Matching and Mapping Function Optimization. ICME Shih-Wei Hsieh, Chih-Hsiang Yang, Yi-Chang Lu
2021	—	`conf`	3D-GFE: a Three-Dimensional Geometric-Feature Extractor for Point Cloud Data. APSIPA ASC Yu-Chen Chou, Yen-Po Lin, Yang-Ming Yeh, Yi-Chang Lu
2021	C	`conf`	A Memory-Efficient Accelerator for DNA Sequence Alignment with Two-Piece Affine Gap Tracebacks. ISCAS Jing-Ping Wu, Yi-Chien Lin, Ying-Wei Wu, Shih-Wei Hsieh, Ching-Hsuan Tai, Yi-Chang Lu
2021	J	`jnl`	A Memory-Efficient FM-Index Constructor for Next-Generation Sequencing Applications on FPGAs. CoRR Nae-Chyun Chen, Yu-Cheng Li, Yi-Chang Lu
2021	—	`conf`	A Real Time Video Stabilizer Based on Feature Trajectories and Global Mesh Warping. APCCAS Sheng-Jui Huang, Yi-Hsien Lin, Chi-Hung Weng, Yi-Chang Lu
2021	—	`conf`	Attention EdgeConv For 3D Point Cloud Classification. APSIPA ASC Yen-Po Lin, Yang-Ming Yeh, Yu-Chen Chou, Yi-Chang Lu
2021	A	`conf`	Power Reduction of a Set-Associative Instruction Cache Using a Dynamic Early Tag Lookup. DATE Chun-Chang Yu, Yu Hen Hu, Yi-Chang Lu, Charlie Chung-Ping Chen
2021	C	`conf`	Using Regularity Unit As Guidance For Summarization-Based Image Resizing. VCIP Fang-Tsung Hsiao, Yi-Hsien Lin, Yi-Chang Lu
2020	C	`conf`	An Image Deblurring Processor for Chromatic Aberration Based on the Primal-Dual Algorithm with Cross-Channel Prior. ISCAS Chia-Han Huang, Yi-Chang Lu
2020	C	`conf`	Comprehensive Study of Keywords for Sequence-Based Automatic Annotation of Protein Functions. BIBE Yu-Cheng Li, Mao-Jan Lin, Xiao-Xuan Huang, Chien-Yu Chen, Yi-Chang Lu
2020	C	`conf`	HDR Deghosting Using Motion-Registration-Free Fusion in the Luminance Gradient Domain. VCIP Cheng-Yeh Liou, Cheng-Yen Chuang, Chia-Han Huang, Yi-Chang Lu
2020	—	`conf`	Hardware Architecture and Implementation of Clustered Tensor Approximation for Multi-Dimensional Visual Data. VLSI-DAT Chi-Yun Yang, Yang-Ming Yeh, Yi-Chang Lu
2019	C	`conf`	A Special-Purpose Processor for FFT-Based Digital Refocusing using 4-D Light Field Data. ISCAS Man-Rong Chen, Hao-Wei Liu, Yi-Hsien Lin, Yi-Chang Lu
2019	J	`jnl`	BLASTP-ACC: Parallel Architecture and Hardware Accelerator Design for BLAST-Based Protein Sequence Alignment. IEEE Trans. Biomed. Circuits Syst. Yu-Cheng Li, Yi-Chang Lu
2019	C	`conf`	Banded Pair-HMM Algorithm for DNA Variant Calling and Its Hardware Accelerator Design. BIBE Ming-Hung Chen, Mao-Jan Lin, Yu-Cheng Li, Yi-Chang Lu
2019	—	`conf`	Colorization of High-Frame-Rate Monochrome Videos Using Synchronized Low-Frame-Rate Color Data. CCIW Ching-Fan Chiang, Yang-Ming Yeh, Chi-Yun Yang, Yi-Chang Lu
2019	—	`conf`	Hardware Accelerator Design for Dynamic-Programming-Based Protein Sequence Alignment with Affine Gap Tracebacks. BioCAS Mao-Jan Lin, Yu-Cheng Li, Yi-Chang Lu
2018	C	`conf`	A High Dynamic Range Light Field Camera and Its Built-In Data Processor Design. ISCAS Po-Hsiang Hsu, Yang-Ming Yeh, Chi-Ming Yeh, Yi-Chang Lu
2018	C	`conf`	A Hybrid Flow for Multiple Sequence Alignment with a BLASTn Based Pairwise Alignment Processor. ISCAS Mao-Jan Lin, Chih-Yu Chang, Yu-Cheng Li, Nae-Chyun Chen, Yi-Chang Lu
2018	C	`conf`	A Memory-Efficient FM-Index Constructor for Next-Generation Sequencing Applications on FPGAs. ISCAS Nae-Chyun Chen, Yu-Cheng Li, Yi-Chang Lu
2018	—	`conf`	Adaptively Banded Smith-Waterman Algorithm for Long Reads and Its Hardware Accelerator. ASAP Yi-Lun Liao, Yu-Cheng Li, Nae-Chyun Chen, Yi-Chang Lu
2018	—	`conf`	An FPGA-Based Liquid Association Calculator for Genome-Wide Co-Expression Analysis. DSP Chien-An Wang, Sheng-Jui Huang, Yu-Cheng Li, Yi-Chang Lu
2018	B	`conf`	Subpixel-Level-Accurate Algorithm for Removing Double-Layered Reflections from a Single Image. ICIP Shih-Wei Hsieh, Yao-Cheng Yang, Chi-Ming Yeh, Sheng-Jui Huang, Yi-Chang Lu
2018	—	`conf`	Three-Dimensional Dynamic Programming Accelerator for Multiple Sequence Alignment. NORCAS Ruei-Ting Chien, Yi-Lun Liao, Chien-An Wang, Yu-Cheng Li, Yi-Chang Lu
2017	A*	`conf`	Deep Co-occurrence Feature Learning for Visual Object Recognition. CVPR Ya-Fang Shih, Yang-Ming Yeh, Yen-Yu Lin, Ming-Fang Weng, Yi-Chang Lu, Yung-Yu Chuang
2016	—	`conf`	A special processor design for Nucleotide Basic Local Alignment Search Tool with a new Banded two-hit method. NORCAS Chih-Yu Chang, Yu-Cheng Li, Nae-Chyun Chen, Xiao-Xuan Huang, Yi-Chang Lu
2016	—	`conf`	An FPGA-based quality filter for de novo sequence assembly pipeline. APCCAS Chun-Shen Liu, Nae-Chyun Chen, Yu-Cheng Li, Yi-Chang Lu
2016	—	`conf`	An iterative re-weighted least squares processor design for deblurring parabolic camera images. GCCE Yu-Hsiang Kao, Sheng-Jui Huang, Yi-Chang Lu
2016	—	`conf`	An orthogonal matching pursuit processor for sparse-representation-based light field data compression. GCCE Yang-Ming Yeh, Chi-Ming Yeh, Ying-Yu Tseng, Yi-Chang Lu
2016	—	`conf`	Mask design for pinhole-array-based hand-held light field cameras with applications in depth estimation. APSIPA Che-Wei Chang, Min-Hung Chen, Kuan-Chang Chen, Chi-Ming Yeh, Yi-Chang Lu
2016	—	`conf`	Non-photorealistic rendering from real video sequences with discontinuity reduction using fast video segmentation. ISOCC Lu Xiao, Xiao-Xuan Huang, Yi-Chang Lu
2016	—	`conf`	Queue-based segmentation algorithm for refining depth maps in light field camera applications. GCCE Yi-Hsiang Chen, Nae-Chyun Chen, Yu-Hsiang Kao, Yu-Cheng Li, Yi-Chang Lu
2016	—	`conf`	Step shift: A fast image segmentation algorithm and its hardware implementation for next-generation sequencing fluorescence data. APCCAS Xiao-Xuan Huang, Chun-Hsien Ho, Yu-Cheng Li, Nae-Chyun Chen, Yi-Chang Lu
2015	—	`conf`	Power efficient special processor design for burrows-wheeler-transform-based short read sequence alignment. BioCAS Nae-Chyun Chen, Tai-Yin Chiu, Yu-Cheng Li, Yu-Chun Chien, Yi-Chang Lu
2015	—	`conf`	Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs. RACS Yi-Jung Chen, Chia-Lin Yang, Ping-Sheng Lin, Yi-Chang Lu
2014	C	`conf`	A pixel-based depth estimation algorithm and its hardware implementation for 4-D light field data. ISCAS Che-Wei Chang, Man-Rong Chen, Po-Hsiang Hsu, Yi-Chang Lu
2014	—	`conf`	Depth estimation for hand-held light field cameras under low light conditions. IC3D Min-Hung Chen, Ching-Fan Chiang, Yi-Chang Lu
2014	J	`jnl`	Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits. IEEE Trans. Very Large Scale Integr. Syst. Chun-Yi Kuo, Chi-Jih Shih, Yi-Chang Lu, James Chien-Mo Li, Krishnendu Chakrabarty
2013	—	`conf`	A power-efficient asynchronous circuit style with selective input-channel restoring. MWSCAS Chin-Khai Tang, Yi-Chang Lu
2013	—	`conf`	Analysis and implementation of Discrete Wavelet Transform for compressing four-dimensional light field data. SoCC Chun-Liang Kuo, Yang-Yao Lin, Yi-Chang Lu
2013	—	`conf`	Architecture and circuit design of parallel processing elements for de novo sequence assembly. SoCC Yulong Huang, Chun-Shen Liu, Yu-Cheng Li, Yi-Chang Lu
2013	A	`conf`	Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs. ISLPED Ping-Sheng Lin, Yi-Jung Chen, Chia-Lin Yang, Yi-Chang Lu
2013	—	`conf`	Light field data processor design for depth estimation using confidence-assisted disparities. SoCC Shih-Chieh Fan Chiang, Po-Hsiang Hsu, Yi-Chang Lu
2013	J	`jnl`	LineDiff Entropy: Lossless Layout Data Compression Scheme for Maskless Lithography Systems. IEEE Signal Process. Lett. Chin-Khai Tang, Ming-Shing Su, Yi-Chang Lu
2013	Misc	`conf`	Parallel architecture and hardware implementation of pre-processor and post-processor for sequence assembly. ICASSP Yuan-Hsiang Kuo, Chun-Shen Liu, Yu-Cheng Li, Yi-Chang Lu
2013	—	`conf`	Power distribution network modeling for 3-D ICs with TSV arrays. ASP-DAC Chi-Kai Shen, Yi-Chang Lu, Yih-Peng Chiou, Tai-Yu Cheng, Tzong-Lin Wu
2013	—	`conf`	Test Generation of Path Delay Faults Induced by Defects in Power TSV. Asian Test Symposium Chi-Jih Shih, Shih-An Hsieh, Yi-Chang Lu, James Chien-Mo Li, Tzong-Lin Wu, Krishnendu Chakrabarty
2013	—	`conf`	Thermal coupling aware task migration using neighboring core search for many-core systems. VLSI-DAT Hitoshi Mizunuma, Yi-Chang Lu, Chia-Lin Yang
2011	J	`jnl`	Thermal Modeling and Analysis for 3-D ICs With Integrated Microchannel Cooling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hitoshi Mizunuma, Yi-Chang Lu, Chia-Lin Yang
2010	—	`conf`	A new method to improve accuracy of parasitics extraction considering sub-wavelength lithography effects. ASP-DAC Kuen-Yu Tsai, Wei-Jhih Hsieh, Yuan-Ching Lu, Bo-Sen Chang, Sheng-Wei Chien, Yi-Chang Lu
2010	B	`conf`	Depth estimation of light field data from pinhole-masked DSLR cameras. ICIP Chih-Chieh Chen, Shih-Chieh Fan Chiang, Xiao-Xuan Huang, Ming-Shing Su, Yi-Chang Lu
2010	Misc	`conf`	Light field based digital refocusing using a DSLR camera with a pinhole array mask. ICASSP Chih-Chieh Chen, Yi-Chang Lu, Ming-Shing Su
2010	—	`conf`	Thermal-aware router-sharing architecture for 3D Network-on-Chip designs. APCCAS Yong-Ruei Huang, Jia-Hong Pan, Yi-Chang Lu
2009	A	`conf`	Thermal modeling for 3D-ICs with integrated microchannel cooling. ICCAD Hitoshi Mizunuma, Chia-Lin Yang, Yi-Chang Lu
2008	A	`conf`	A new method to improve accuracy of leakage current estimation for transistors with non-rectangular gates due to sub-wavelength lithography effects. ICCAD Kuen-Yu Tsai, Meng-Fu You, Yi-Chang Lu, Philip C. W. Ng
2008	—	`conf`	An Asynchronous Circuit Design with Fast Forwarding Technique at Advanced Technology Node. ISQED Chin-Khai Tang, Chun-Yen Lin, Yi-Chang Lu
2007	J	`jnl`	A Built-in Technique for Measuring Substrate and Power-Supply Digital Switching Noise Using PMOS-Based Differential Sensors and a Waveform Sampler in System-on-Chip Applications. IEEE Trans. Instrum. Meas. Cosmin Iorga, Yi-Chang Lu, Robert W. Dutton
2007	J	`jnl`	Performance Benefits of Monolithically Stacked 3-D FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, S. Simon Wong
2006	A	`conf`	Performance benefits of monolithically stacked 3D-FPGA. FPGA Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, S. Simon Wong
2004	—	`conf`	Modeling of Wave Behavior of Substrate Noise Coupling for Mixed-Signal IC Design. ISQED Georgios Veronis, Yi-Chang Lu, Robert W. Dutton
2001	—	`conf`	A fast analytical technique for estimating the bounds of on-chip clock wire inductance. CICC Yi-Chang Lu, Kaustav Banerjee, Mustafa Celik, Robert W. Dutton
2001	A*	`conf`	Min/max On-Chip Inductance Models and Delay Metrics. DAC Yi-Chang Lu, Mustafa Celik, Tak Young, Lawrence T. Pileggi