Yervant Zorian

276 papers A* 9A 69B 6C 15Misc 32Journal 86Unranked 56

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Test, Debug, and Silicon Lifecycle Management Architecture for a UCIe-Based Open Chiplet Ecosystem. IEEE Micro Sridhar Muthrasanallur, Yervant Zorian
2025	B	`conf`	Analysis and Mitigation of Radiation Effects in SRAM-based Register Files. ETS Zhe Zhang, Surendra Hemaram, Mahta Mayahinia, Christian Weis, Norbert Wehn, Mehdi B. Tahoori, Sani R. Nassif, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian
2025	B	`conf`	European Test Symposium Teams: an Anniversary Snapshot. ETS Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilárd Enyedi, I. Stefan, Ovidiu Stan, Cosmina Corches, Z. Peng, Petru Eles, Rolf Drechsler, S. Eggersglüß, Görschwin Fey, Andreas Glowatz, Daniel Tille, Georges G. E. Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, P.-Y. Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi, S. Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, P. Girard, Marcello Traiola, Arnaud Virazel, F. Fernandes Dos Santos, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letícia Maria Bolzani Poehls, Milos Krstic, Marko S. Andjelkovic, F. Vargas, Grigor Tshagharyan, Gurgen Harutyunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, A. Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zain Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand
2025	A	`conf`	Leveraging UCIe Interface for Silicon Health & Reliabiilty of Chiplets in a 3D Stack. ITC Sandeep Kumar Goel, Ankita Patidar, Stanley John, Frank Lee, Min-Jer Wang, Daniel F. J. Yang, Yervant Zorian, Manish Arora, Firooz Massoudi, Shaan Awasthi, Stelios Balalis, Velmurugan Pathervellaichamy, Bharath Shankaranarayanan, Narasimhalu Raju, Gurgen Harutyunyan, Grigor Tshagharyan, Vahagn Hovakimyan, Arman Karagyozyan, Alvina Manucharyan
2025	J	`jnl`	Silicon Lifecycle Management (SLM): Requirements, Trends, and Opportunities. IEEE Des. Test Mehdi Baradaran Tahoori, Seyedeh Maryam Ghasemi, Yervant Zorian
2024	Misc	`conf`	Addressing the Combined Effect of Transistor and Interconnect Aging in SRAM towards Silicon Lifecycle Management. VTS Zhe Zhang, Mahta Mayahinia, Christian Weis, Norbert Wehn, Mehdi B. Tahoori, Sani R. Nassif, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian
2024	—	`conf`	An Approach for Increasing Memory Repair Efficiency. EWDTS Karen Amirkhanyan, A. Babayan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian
2024	J	`jnl`	Functionally Possible Path Delay Faults With High Functional Switching Activity. IEEE Trans. Very Large Scale Integr. Syst. Irith Pomeranz, Yervant Zorian
2024	C	`conf`	On-Chip Sensor to Monitor Aging Evolution in FinFET-Based Memories. IOLTS Fabian Vargas, Vache Galstyan, Gurgen Harutyunyan, Yervant Zorian
2024	—	`conf`	Repair of Resistive Open Defects on Word-Lines and Bit-Lines of SRAMs. EWDTS Karen Amirkhanyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian
2024	J	`jnl`	Special Issue on Silicon Lifecycle Management. IEEE Des. Test Mehdi Baradaran Tahoori, Yervant Zorian
2024	J	`jnl`	Testing for Electromigration in Sub-5-nm FinFET Memories. IEEE Des. Test Mahta Mayahinia, Mehdi Baradaran Tahoori, Grigor Tshagharyan, Karen Amirkhanyan, Artur Ghukasyan, Gurgen Harutyunyan, Yervant Zorian
2024	A	`conf`	Testing for aging in advanced SRAM: From front end of the line transistors to back end of the line interconnects. ITC Zhe Zhang, Mahta Mayahinia, Christian Weis, Norbert Wehn, Mehdi B. Tahoori, Sani R. Nassif, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian
2023	Misc	`conf`	Innovation Practices Track: Silicon Lifecycle Management Challenges and Opportunities. VTS Fei Su, Xiankun Robert Jin, Nilanjan Mukherjee, Yervant Zorian
2023	B	`conf`	On-chip Electromigration Sensor for Silicon Lifecycle Management of Nanoscale VLSI. ETS Mahta Mayahinia, Mehdi Baradaran Tahoori, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian
2023	Misc	`conf`	Overcoming Embedded Memory Test & Repair Challenges in the Gate-All-Around Era. VTS Artur Ghukasyan, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian
2023	A	`conf`	SLM Subsystem for Automotive SoC: Case Study on Path Margin Monitor. ITC Kranthi Kandula, Ramalingam Kolisetti, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian
2023	—	`conf`	Silicon Lifecycle Management: Trends, Challenges and Solutions : Tutorial 2. ITC-Asia Yervant Zorian
2023	A	`conf`	Utilizing ECC Analytics to Improve Memory Lifecycle Management. ITC Costas Argyrides, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian
2022	A	`conf`	A Novel Protection Technique for Embedded Memories with Optimized PPA. ITC Costas Argyrides, Vilas Sridharan, Hayk Danoyan, Gurgen Harutyunyan, Yervant Zorian
2022	Misc	`conf`	Innovative Practices Track: What's Next for Automotive: Where and How to Improve Field Test and Enhance SoC Safety. VTS Minqiang Peng, Youfa Wu, Jialiang Li, Alex Yu, Grigor Tshagharyan, Costas Argyrides, Vilas Sridharan, Gurgen Harutyunyan, Yervant Zorian, Nilanjan Mukherjee
2021	—	`conf`	Automotive Test and Reliability. ITC-Asia Yu Huang, David Francis, Yervant Zorian, Nilanjan Mukherjee
2020	J	`jnl`	Memory Physical Aware Multi-Level Fault Diagnosis Flow. IEEE Trans. Emerg. Top. Comput. Gurgen Harutyunyan, Suren Martirosyan, Samvel K. Shoukourian, Yervant Zorian
2020	A	`conf`	Test and Diagnosis Solution for Functional Safety. ITC M. Casarsa, Gurgen Harutyunyan, Yervant Zorian
2019	A	`conf`	17th IEEE East-West Design and Test Symposium. ITC Yervant Zorian, Vladimir Hahanov, Svetlana Chumachenko, Eugenia Litvinova
2019	J	`jnl`	Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gurgen Harutyunyan, Samvel K. Shoukourian, Yervant Zorian
2019	Misc	`conf`	Innovative Practices on In-System Test and Reliability of Memories. VTS S. Bandyopadhyay, J. Mekkoth, Marc Hutner, Hayk T. Grigoryan, Arun Kumar, Samvel K. Shoukourian, Grigor Tshagharyan, Yervant Zorian, Gabriele Boschi, Duccio Lazzarotti, Donato Luongo, Hanna Shaheen, Gurgen Harutyunyan
2019	A	`conf`	International Test Conference in Asia (ITC-Asia) - Bridging ITC and Test Community in Asia. ITC Kuen-Jong Lee, Shi-Yu Huang, Huawei Li, Tomoo Inoue, Yervant Zorian
2019	A	`conf`	Memory FIT Rate Mitigation Technique for Automotive SoCs. ITC Gabriele Boschi, Donato Luongo, Duccio Lazzarotti, Hanna Shaheen, Hayk T. Grigoryan, Gurgen Harutyunyan, Samvel K. Shoukourian, Yervant Zorian
2019	—	`conf`	Trends & Challenges in Today's Automotive SOCs. MECO Yervant Zorian
2018	A	`conf`	Advanced ECC-Based FIT Rate Mitigation Technique for Automotive SoCs. ITC Hayk T. Grigoryan, Samvel K. Shoukourian, Gurgen Harutyunyan, Yervant Zorian, Costas Argyrides
2018	A	`conf`	Advanced Uniformed Test Approach For Automotive SoCs. ITC Tal Kogan, Yehonatan Abotbol, Gabriele Boschi, Gurgen Harutyunyan, N. Martirosyan, Yervant Zorian
2018	A	`conf`	Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM. ITC Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori, Grigor Tshagharyan, Hayk T. Grigoryan, Gurgen Harutyunyan, Yervant Zorian
2018	J	`jnl`	Guest Editor's Introduction. IEEE Des. Test Hans-Joachim Wunderlich, Yervant Zorian
2018	Misc	`conf`	IP session on ISO26262 EDA. VTS Art Schaldenbrand, Yervant Zorian, Stephen Sunter, Peter Sarson
2018	A	`conf`	Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications. ITC Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian, Anteneh Gebregiorgis, Mohammad Saber Golanbari, Rajendra Bishnoi, Mehdi Baradaran Tahoori
2018	J	`jnl`	The 10th China Test Conference. IEEE Des. Test Yervant Zorian
2017	C	`conf`	Advanced ECC solution for automotive SoCs. IOLTS Hanna Shaheen, Gabriele Boschi, Gurgen Harutyunyan, Yervant Zorian
2017	A	`conf`	Advanced functional safety mechanisms for embedded memories and IPs in automotive SoCs. ITC Tal Kogan, Yehonatan Abotbol, Gabriele Boschi, Gurgen Harutyunyan, I. Kroul, Hanna Shaheen, Yervant Zorian
2017	C	`conf`	An effective functional safety infrastructure for system-on-chips. IOLTS Christophe Eychenne, Yervant Zorian
2017	A	`conf`	An effective functional safety solution for automotive systems-on-chip. ITC Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian
2017	—	`conf`	An efficient testing methodology for embedded flash memories. EWDTS Suren Martirosyan, Gurgen Harutyunyan, Samvel K. Shoukourian, Yervant Zorian
2017	—	`conf`	Automated flow for test pattern creation for IPs in SoC. EWDTS D. Sargsyan, Gurgen Harutyunyan, Samvel K. Shoukourian, Yervant Zorian
2017	—	`conf`	Experimental study on Hamming and Hsiao codes in the context of embedded applications. EWDTS Grigor Tshagharyan, Gurgen Harutyunyan, Samvel K. Shoukourian, Yervant Zorian
2017	J	`jnl`	Guest Editors' Introduction: Design & Test of a High-Volume 3-D Stacked Graphics Processor With High-Bandwidth Memory. IEEE Des. Test Erik Jan Marinissen, Yervant Zorian
2017	C	`conf`	Keynotes: Robustness challenges in the internet of things. VLSI-SoC Yervant Zorian
2017	—	`conf`	Tutorial I: Topic: Automotive test strategies. ITC-Asia Yervant Zorian
2016	B	`conf`	IoT: Source of test challenges. ETS Erik Jan Marinissen, Yervant Zorian, Mario Konijnenburg, Chih-Tsun Huang, Ping-Hsuan Hsieh, Peter Cockburn, Jeroen Delvaux, Vladimir Rozic, Bohan Yang, Dave Singelée, Ingrid Verbauwhede, Cedric Mayor, Robert Van Rijsinge, Cocoy Reyes
2016	—	`conf`	Securing test infrastructure of system-on-chips. EWDTS Grigor Tshagharyan, Gurgen Harutyunyan, Samvel K. Shoukourian, Yervant Zorian
2016	—	`conf`	Welcome to the IDT 2016. IDT Mohamed Abid, Yervant Zorian
2015	—	`conf`	A power based memory BIST grouping methodology. EWDTS L. Martirosyan, Gurgen Harutyunyan, Samvel K. Shoukourian, Yervant Zorian
2015	C	`conf`	An effective embedded test & diagnosis solution for external memories. IOLTS Gurgen Harutunyan, Yervant Zorian
2015	—	`conf`	An efficient approach for memory repair by reducing the number of spares. EWDTS Vrezh Sargsyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Avetik Yessayan
2015	—	`ed.`	Collaboration and Technology - 21st International Conference, CRIWG 2015, Yerevan, Armenia, September 22-25, 2015, Proceedings CRIWG Nelson Baloian, Yervant Zorian, Perouz Taslakian, Samvel K. Shoukourian
2015	Misc	`conf`	Impact of parameter variations on FinFET faults. VTS Gurgen Harutyunyan, Grigor Tshagharyan, Yervant Zorian
2015	—	`conf`	Keynote 3: "Ensuring robustness in today's IoT era". IDT Yervant Zorian
2015	—	`conf`	Message from the LATS2015 Chairs. LATS Víctor H. Champac, Yervant Zorian, Letícia Maria Bolzani Pöhls, Vishwani D. Agrawal
2015	—	`conf`	Overview study on fault modeling and test methodology development for FinFET-based memories. EWDTS Grigor Tshagharyan, Gurgen Harutyunyan, Samvel K. Shoukourian, Yervant Zorian
2015	C	`conf`	The future of fault tolerant computing. IOLTS Jacob A. Abraham, Ravishankar K. Iyer, Dimitris Gizopoulos, Dan Alexandrescu, Yervant Zorian
2014	A	`conf`	Design, test & repair methodology for FinFET-based memories. ITC Yervant Zorian
2014	—	`conf`	Extending fault periodicity table for testing faults in memories under 20nm. EWDTS Gurgen Harutyunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian
2014	Misc	`conf`	Fault modeling and test algorithm creation strategy for FinFET-based memories. VTS Gurgen Harutyunyan, Grigor Tshagharyan, Valery A. Vardanian, Yervant Zorian
2014	J	`jnl`	Guest Editors' Introduction: Highlights of the 50th DAC. IEEE Des. Test Yervant Zorian, Soha Hassoun
2014	Misc	`conf`	Special session 12C: Young professionals in test - Town meeting. VTS Alodeep Sanyal, Yanjing Li, Yervant Zorian
2013	Misc	`conf`	An effective solution for building memory BIST infrastructure based on fault periodicity. VTS Gurgen Harutyunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian
2013	—	`conf`	An efficient fault diagnosis and localization algorithm for Successive-Approximation Analog to Digital Converters. EWDTS T. Melkumyan, Gurgen Harutyunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian
2013	—	`conf`	Application of defect injection flow for fault validation in memories. EWDTS K. Amirkhanyan, A. Davtyan, Gurgen Harutyunyan, T. Melkumyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian
2013	—	`conf`	Impact of process variations on read failures in SRAMs. EWDTS Gurgen Harutyunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian
2013	C	`conf`	Integrating embedded test infrastructure in SRAM cores to detect aging. IOLTS W. Prates, Letícia Maria Veiras Bolzani, Gurgen Harutyunyan, A. Davtyan, Fabian Vargas, Yervant Zorian
2013	Misc	`conf`	Special session 12C: Town-hall meeting "young professionals in test". VTS Alodeep Sanyal, Yervant Zorian
2012	J	`jnl`	A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gurgen Harutyunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian
2012	—	`conf`	Addressing Test Challenges in Advanced Technology Nodes. Asian Test Symposium Yervant Zorian
2012	A	`conf`	Design for test and reliability in ultimate CMOS. DATE Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep P. Kulkarni, Vivek De, Dimiter Avresky
2012	J	`jnl`	Guest Editorial: Special Issue on Testing of 3D Stacked Integrated Circuits. J. Electron. Test. Erik Jan Marinissen, Yervant Zorian
2012	J	`jnl`	Message From the Steering Committee. IEEE Des. Test Comput. P. Glenn Gulak, Rajesh Gupta, Gianluca Setti, Yervant Zorian
2011	J	`jnl`	12th "IEEE Latin-American Test Workshop" Porto de Galinhas, Brazil, 27-30 March 2011. J. Low Power Electron. Víctor H. Champac, Fernanda Gusmão de Lima Kastensmidt, Letícia Maria Veiras Bolzani Poehls, Fabian Vargas, Yervant Zorian
2011	—	`ed.`	9th East-West Design & Test Symposium, EWDTS 2011, Sevastopol, Ukraine, September 9-12, 2011 EWDTS Vladimir Hahanov, Yervant Zorian
2011	—	`conf`	A Robust Solution for Embedded Memory Test and Repair. Asian Test Symposium K. Darbinyan, Gurgen Harutyunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian
2011	C	`conf`	Generic BIST architecture for testing of content addressable memories. IOLTS Hayk T. Grigoryan, Gurgen Harutunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian
2011	J	`jnl`	Symmetry Measure for Memory Test and Its Application in BIST Optimization. J. Electron. Test. Gurgen Harutunyan, Aram Hakhumyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian
2010	—	`ed.`	5th International Design and Test Workshop, IDT 2010, Abu Dhabi, UAE, 14-15 December 2010 IDT Yervant Zorian, Imtinan Elahi, André Ivanov, Ashraf Salem
2010	—	`conf`	An efficient March test for detection of all two-operation dynamic faults from subclass Sav. EWDTS H. Avetisyan, Gurgen Harutyunyan, Valery A. Vardanian, Yervant Zorian
2010	C	`conf`	Test and reliability concerns for 3D-ICs. IOLTS Yervant Zorian
2009	A*	`conf`	DFM: don't care or competitive weapon? DAC Mark Redford, Joseph Sawicki, Prasad Subramaniam, Cliff Hou, Yervant Zorian, Kimon Michaels
2009	J	`jnl`	Guest Editor's Introduction: Examples of Management Decision Criteria. IEEE Des. Test Comput. Yervant Zorian
2009	J	`jnl`	Guest Editors' Introduction: The Status of IEEE Std 1500 - Part 2. IEEE Des. Test Comput. Erik Jan Marinissen, Yervant Zorian
2009	J	`jnl`	Guest Editors' Introduction: The Status of IEEE Std 1500. IEEE Des. Test Comput. Erik Jan Marinissen, Yervant Zorian
2009	J	`jnl`	IEEE Std 1500 Enables Modular SoC Testing. IEEE Des. Test Comput. Erik Jan Marinissen, Yervant Zorian
2009	A	`conf`	Panel Session - Vertical integration versus disaggregation. DATE Yervant Zorian
2009	A	`conf`	Testing 3D chips containing through-silicon vias. ITC Erik Jan Marinissen, Yervant Zorian
2008	Misc	`conf`	An Efficient March-Based Three-Phase Fault Location and Full Diagnosis Algorithm for Realistic Two-Operation Dynamic Faults in Random Access Memories. VTS Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian
2008	J	`jnl`	IEEE Standard 1500 Compliance Verification for Embedded Cores. IEEE Trans. Very Large Scale Integr. Syst. Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Yervant Zorian
2007	C	`conf`	A March-based Fault Location Algorithm with Partial and Full Diagnosis for All Simple Static Faults in Random Access Memories. DDECS Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian
2007	A*	`conf`	Making Manufacturing Work For You. DAC Srikanth Venkataraman, Ruchir Puri, Steve Griffith, Ankush Oberai, Robert Madge, Greg Yeric, Walter Ng, Yervant Zorian
2007	J	`jnl`	Minimal March Tests for Detection of Dynamic Faults in Random Access Memories. J. Electron. Test. Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian
2007	—	`conf`	Next Generation Test, Diagnostics and Yield Challenges for EDA, ATE, IP and Fab - A Perspective from All Sides. ATS Yasuharu Kohiyama, C. P. Ravikumar, Yasuo Sato, Laung-Terng Wang, Yervant Zorian
2006	A*	`conf`	Decision-making for complex SoCs in consumer electronic products. DAC Ron Wilson, Yervant Zorian
2006	J	`jnl`	Guest Editors' Introduction: Big Innovations in Small Packages. IEEE Des. Test Comput. Bruce C. Kim, Yervant Zorian
2006	Misc	`conf`	Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access Memories. VTS Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian
2006	B	`conf`	Minimal March Tests for Dynamic Faults in Random Access Memories. ETS Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian
2006	C	`conf`	Minimal March-Based Fault Location Algorithm with Partial Diagnosis for all Static Faults in Random Access Memories. DDECS Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian
2006	Misc	`conf`	Session Abstract. VTS Yervant Zorian, Bruce C. Kim
2006	Misc	`conf`	Session Abstract. VTS Yervant Zorian, Dennis Wassung
2006	A*	`conf`	Tradeoffs and choices for emerging SoCs in high-end applications. DAC Nic Mokhoff, Yervant Zorian
2005	A	`conf`	Challenges in Embedded Memory Design and Test. DATE Erik Jan Marinissen, Betty Prince, Doris Keitel-Schulz, Yervant Zorian
2005	A*	`conf`	Choosing flows and methodologies for SoC design. DAC Dennis Wassung, Yervant Zorian, Magdy S. Abadir, Mark Bapst, Colin Harris
2005	J	`jnl`	Guest Editors' Introduction: DFM Drives Changes in Design Flow. IEEE Des. Test Comput. Juan Antonio Carballo, Yervant Zorian, Raul Camposano, Andrzej J. Strojwas, John Kibarian, Dennis Wassung, Alex Alexanian, Steve Wigley, Neil Kelly
2005	A*	`conf`	How to determine the necessity for emerging solutions. DAC Nic Mokhoff, Yervant Zorian, Kamalesh N. Ruparel, Hao Nham, Francesco Pessolano, Kee Sup Kim
2005	A	`conf`	IEEE 1500 utilization in SOC design and test. ITC Yervant Zorian, Avetik Yessayan
2005	C	`conf`	Impact of Soft Error Challenge on SoC Design. IOLTS Yervant Zorian, Valery A. Vardanian, K. Aleksanyan, K. Amirkhanyan
2005	Misc	`conf`	Minimal March Tests for Unlinked Static Faults in Random Access Memories. VTS Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian
2005	J	`jnl`	Nanoscale Design & Test Challenges. Computer Yervant Zorian
2005	C	`conf`	On-Line Testing for Secure Implementations: Design and Validation. IOLTS Régis Leveugle, Yervant Zorian, Luca Breveglieri, André K. Nieuwland, Klaus Rothbart, Jean-Pierre Seifert
2005	Misc	`conf`	Optimizing SoC Manufacturability. VLSI Design Yervant Zorian
2005	Misc	`conf`	SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms. VTS Baosheng Wang, Yuejian Wu, Josh Yang, André Ivanov, Yervant Zorian
2005	A	`conf`	Semiconductor Industry Disaggregation vs Reaggregation: Who Will be the Shark? DATE Yervant Zorian, Bill Frerichs, Dennis Wassung, Jim Ensel, Guri Stark, Mike Gianfagna, Kamalesh N. Ruparel
2005	—	`conf`	T1: Design for Manufacturability. Asian Test Symposium Yervant Zorian, Juan Antonio Carballo
2005	A	`conf`	Today's SOC test challenges. ITC Yervant Zorian
2004	J	`jnl`	2003 Technology Roadmap for Semiconductors. Computer Don Edenfeld, Andrew B. Kahng, Mike Rodgers, Yervant Zorian
2004	Misc	`conf`	A Methodology for Design and Evaluation of Redundancy Allocation Algorithms. VTS Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian
2004	J	`jnl`	Design & Test Education in Asia. IEEE Des. Test Comput. Debesh K. Das, Hideo Fujiwara, Yungang Li, Yinghua Min, Shiyi Xu, Yervant Zorian
2004	J	`jnl`	Distributed Diagnosis of Interconnections in SoC and MCM Designs. J. Electron. Test. Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian
2004	—	`conf`	Embedded Memory Reliability: The SER Challenge. MTDT N. Derhacobian, Valery A. Vardanian, Yervant Zorian
2004	J	`jnl`	Fault isolation for nonisolated blocks. IEEE Trans. Very Large Scale Integr. Syst. Irith Pomeranz, Yervant Zorian
2004	J	`jnl`	Guest Editors' Introduction: Design for Yield and Reliability. IEEE Des. Test Comput. Yervant Zorian, Dimitris Gizopoulos, Cary Vandenberg, Philippe Magarshack
2004	A	`conf`	Investment vs. Yield Relationship for Memories in SOC. ITC Yervant Zorian
2004	Misc	`conf`	Reducing Embedded SRAM Test Time under Redundancy Constraints. VTS Baosheng Wang, Josh Yang, James Cicalo, André Ivanov, Yervant Zorian
2004	J	`jnl`	SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure. IEEE Des. Test Comput. Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian
2003	J	`jnl`	A Hierarchical Infrastructure for SoC Test Management. IEEE Des. Test Comput. Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Yervant Zorian
2003	Misc	`conf`	A Test Interface for Built-In Test of Non-Isolated Scanned Cores. VTS Irith Pomeranz, Sudhakar M. Reddy, Yervant Zorian
2003	A	`conf`	Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores. ITC Nektarios Kranitis, George Xenoulis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian
2003	J	`jnl`	Easily Testable Cellular Carry Lookahead Adders. J. Electron. Test. Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian
2003	J	`jnl`	Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield. IEEE Des. Test Comput. Yervant Zorian, Samvel K. Shoukourian
2003	J	`jnl`	Guest Editor's Introduction: Advances in Infrastructure IP. IEEE Des. Test Comput. Yervant Zorian
2003	J	`jnl`	IEEE CASS becomes D&T Copublisher. IEEE Des. Test Comput. Yervant Zorian
2003	J	`jnl`	Instruction-Based Self-Testing of Processor Cores. J. Electron. Test. Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian
2003	—	`conf`	Leveraging Infrastructure IP for SoC Yield. Asian Test Symposium Yervant Zorian
2003	A	`conf`	Low-Cost Software-Based Self-Testing of RISC Processor Cores. DATE Nektarios Kranitis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
2003	A	`conf`	Overview of the IEEE P1500 Standard. ITC Francisco DaSilva, Yervant Zorian, Lee Whetsel, Karim Arabi, Rohit Kapur
2003	A	`conf`	Yield Threats and Inadequacy of One-time Test. ITC Yervant Zorian
2002	J	`jnl`	2001 Technology Roadmap for Semiconductors. Computer Alan Allan, Don Edenfeld, William H. Joyner Jr., Andrew B. Kahng, Mike Rodgers, Yervant Zorian
2002	—	`conf`	A March-Based Fault Location Algorithm for Static Random Access Memories. IOLTW Valery A. Vardanian, Yervant Zorian
2002	—	`conf`	A March-Based Fault Location Algorithm for Static Random Access Memories. MTDT Valery A. Vardanian, Yervant Zorian
2002	A	`conf`	Effective Software Self-Test Methodology for Processor Cores. DATE Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian
2002	A	`conf`	Embedded Memory Test and Repair: Infrastructure IP for SOC Yield. ITC Yervant Zorian
2002	A*	`conf`	Embedding infrastructure IP for SOC yield improvement. DAC Yervant Zorian
2002	A	`conf`	Fault Isolation Using Tests for Non-Isolated Blocks. DATE Irith Pomeranz, Yervant Zorian
2002	Misc	`conf`	Instruction-Based Self-Testing of Processor Cores. VTS Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian
2002	J	`jnl`	On IEEE P1500's Standard for Embedded Core Test. J. Electron. Test. Erik Jan Marinissen, Rohit Kapur, Maurice Lousberg, Teresa L. McLaurin, Mike Ricchetti, Yervant Zorian
2002	—	`conf`	Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA. DELTA Michel Renovell, Penelope Faure, Paolo Prinetto, Yervant Zorian
2001	J	`jnl`	A Discussion on Test Pattern Generation for FPGA - Implemented Circuits. J. Electron. Test. Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian
2001	—	`conf`	An Approach for Evaluation of Redunancy Analysis Algorithms. MTDT Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian
2001	—	`conf`	An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths. ISQED Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
2001	J	`jnl`	An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths. J. Electron. Test. Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Mihalis Psarakis, Yervant Zorian
2001	J	`jnl`	Boundary Scan-Based Relay Wave Propagation Test of Arrays of Identical Structures. IEEE Trans. Computers Koppolu Sasidhar, Abhijit Chatterjee, Yervant Zorian
2001	A	`conf`	Deterministic software-based self-testing of embedded processor cores. DATE Antonis M. Paschalis, Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Yervant Zorian
2001	J	`jnl`	EIC Message. IEEE Des. Test Comput. Yervant Zorian
2001	A	`conf`	Embedded tutorial: TRP: integrating embedded test and ATE. DATE Yervant Zorian, Paolo Prinetto, João Paulo Teixeira, Isabel C. Teixeira, Carlos Eduardo Pereira, Octávio Páscoa Dias, Jorge Semião, Peter Muhmenthaler, W. Radermacher
2001	J	`jnl`	Error-Free Products. IEEE Des. Test Comput. Yervant Zorian
2001	J	`jnl`	Huge Storage Capacity. IEEE Des. Test Comput. Yervant Zorian
2001	A	`conf`	IS-FPGA : a new symmetric FPGA architecture with implicit scan. ITC Michel Renovell, Penelope Faure, Jean-Michel Portal, Joan Figueras, Yervant Zorian
2001	Misc	`conf`	Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers. VTS Mihalis Psarakis, Antonis M. Paschalis, Nektarios Kranitis, Dimitris Gizopoulos, Yervant Zorian
2001	J	`jnl`	Switching activity generation with automated BIST synthesis forperformance testing of interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian
2001	—	`conf`	System-on-Chip: Embedded Test Strategies. ISQED Yervant Zorian
2001	—	`conf`	Testing Embedded Core-Based System Chips. LATW Erik Jan Marinissen, Yervant Zorian
2000	J	`jnl`	A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures. J. Electron. Test. Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian
2000	J	`jnl`	An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family. J. Electron. Test. Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
2000	—	`conf`	Analyzing the test generation problem for an application-oriented test of FPGAs. ETW Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian
2000	—	`conf`	Deterministic Built-In Self -Test for Shifters, Adders and ALUs in Datapaths. LATW Mihalis Psarakis, Nektarios Kranitis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
2000	A	`conf`	Different experiments in test generation for XILINX FPGAs. ITC Michel Renovell, Yervant Zorian
2000	A	`conf`	Effective Low Power BIST for Datapaths. DATE Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian
2000	J	`jnl`	Embedded in this issue. IEEE Des. Test Comput. Yervant Zorian
2000	—	`conf`	Embedded-Quality for Test. ISQED Yervant Zorian
2000	J	`jnl`	Flexibility and Programmability. IEEE Des. Test Comput. Yervant Zorian
2000	A	`conf`	HD ITC Alfredo Benso, Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto, Fabio Ricciato, Maurizio Spadari, Yervant Zorian
2000	Misc	`conf`	Low Power/Energy BIST Scheme for Datapaths. VTS Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian
2000	A	`conf`	On using IEEE P1500 SECT for test plug-n-play. ITC Yervant Zorian, Erik Jan Marinissen, Rohit Kapur
2000	J	`jnl`	Power-/Energy Efficient BIST Schemes for Processor Data Paths. IEEE Des. Test Comput. Nektarios Kranitis, Dimitris Gizopoulos, Antonis M. Paschalis, Mihalis Psarakis, Yervant Zorian
2000	J	`jnl`	Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays. IEEE Trans. Computers Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
2000	—	`conf`	SoC Testing and P1500 Standard. Asian Test Symposium Tsin-Yuan Chang, Yervant Zorian
2000	—	`conf`	Some Experiments in Test Pattern Generation for FPGA-Implemented Combinational Circuits. SBCCI Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian
2000	A*	`conf`	System chip test: how will it impact your design? DAC Yervant Zorian, Erik Jan Marinissen
2000	—	`conf`	TOF: a tool for test pattern generation optimization of an FPGA application oriented test. Asian Test Symposium Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian
2000	—	`conf`	Test Configuration Generation for FPGA Logic Cells. LATW Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
2000	A	`conf`	Test of Future System-on-Chips. ICCAD Yervant Zorian, Sujit Dey, Mike Rodgers
2000	J	`jnl`	Testing the Local Interconnect Resources of SRAM-Based FPGA's. J. Electron. Test. Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
2000	A	`conf`	Tutorial Statement. DATE Yervant Zorian, Michael Nicolaidis, Peter Muhmenthaler, David Y. Lepejian, Chris W. H. Strolenberg, Kees Veelenturf
2000	J	`jnl`	Wider Coverage. IEEE Des. Test Comput. Yervant Zorian
2000	A	`conf`	Wrapper design for embedded core test. ITC Yervant Zorian, Erik Jan Marinissen, Maurice Lousberg, Sandeep Kumar Goel
2000	A	`conf`	Yield Improvement and Repair Trade-Off for Large Embedded Memories. DATE Yervant Zorian
1999	—	`conf`	A high-level EDA environment for the automatic insertion of HD-BIST structures. ETW Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian
1999	A	`conf`	An Effective BIST Architecture for Fast Multiplier Cores. DATE Antonis M. Paschalis, Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Yervant Zorian
1999	Misc	`conf`	An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers. VTS Mihalis Psarakis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian
1999	J	`jnl`	An Effective Built-In Self-Test Scheme for Parallel Multipliers. IEEE Trans. Computers Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
1999	J	`jnl`	Challenges in testing core-based system ICs. IEEE Commun. Mag. Erik Jan Marinissen, Yervant Zorian
1999	J	`jnl`	D&T Expands. IEEE Des. Test Comput. Yervant Zorian
1999	J	`jnl`	Focus on DRAMs. IEEE Des. Test Comput. Yervant Zorian
1999	A	`conf`	HD-BIST: a hierarchical framework for BIST scheduling and diagnosis in SOCs. ITC Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian
1999	J	`jnl`	Integration Continues. IEEE Des. Test Comput. Yervant Zorian
1999	—	`conf`	Minimizing the Number of Test Configurations for Different FPGA Families. Asian Test Symposium Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1999	J	`jnl`	SRAM-Based FPGAs: Testing the Embedded RAM Modules. J. Electron. Test. Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1999	A	`conf`	Scaling Deeper to Submicron: On-Line Testing to the Rescue. DATE Michael Nicolaidis, Yervant Zorian
1999	—	`conf`	Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study. ETW Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1999	J	`jnl`	Testing Embedded-Core-Based System Chips. Computer Yervant Zorian, Erik Jan Marinissen, Sujit Dey
1999	Misc	`conf`	Testing of Non-Isolated Embedded Legacy Cores and their Surrounding Logic. VTS Irith Pomeranz, Yervant Zorian
1999	A	`conf`	Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's. DATE Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1999	A	`conf`	Towards a standard for embedded core test: an example. ITC Yervant Zorian, Erik Jan Marinissen, Rohit Kapur, Tony Taylor, Lee Whetsel
1998	J	`jnl`	A D&T Roundtable: Testing Mixed Logic and DRAM Chips. IEEE Des. Test Comput. Meh-Ron Amerian, William D. Atwell Jr., Ian Burgess, Gary D. Fleeman, David Y. Lepejian, T. W. Williams, Farzad Zarrinfar, Yervant Zorian
1998	A	`conf`	A distributed BIST technique for diagnosis of MCM interconnections. ITC Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian
1998	A	`conf`	Built in self repair for embedded high density SRAM. ITC Ilyoung Kim, Yervant Zorian, Goh Komoriya, Hai Pham, Frank P. Higgins, Jim L. Lewandowski
1998	A	`conf`	Built-In Self-Test with an Alternating Output. DATE T. Bogue, Michael Gössel, Helmut Jürgensen, Yervant Zorian
1998	J	`jnl`	Challenges and Options. IEEE Des. Test Comput. Yervant Zorian
1998	J	`jnl`	D&T: 15th Year in Service. IEEE Des. Test Comput. Yervant Zorian
1998	J	`jnl`	Effective Built-In Self-Test for Booth Multipliers. IEEE Des. Test Comput. Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
1998	J	`jnl`	Efficient Totally Self-Checking Shifter Design. J. Electron. Test. Ricardo de Oliveira Duarte, Michael Nicolaidis, Hakim Bederr, Yervant Zorian
1998	A	`conf`	High-level design validation and test. ICCAD Sujit Dey, Jacob A. Abraham, Yervant Zorian
1998	J	`jnl`	ITC 97 Panel Sessions. IEEE Des. Test Comput. Dilip K. Bhavsar, Yervant Zorian
1998	A	`conf`	Novel Technique for Testing FPGAs. DATE Cecilia Metra, Michel Renovell, Giovanni A. Mojoli, Jean-Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi
1998	J	`jnl`	On-Line Testing for VLSI - A Compendium of Approaches. J. Electron. Test. Michael Nicolaidis, Yervant Zorian
1998	J	`jnl`	Once Again, a Super Issue. IEEE Des. Test Comput. Yervant Zorian
1998	A	`conf`	RAM-Based FPGA's: A Test Approach for the Configurable Logic. DATE Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1998	Misc	`conf`	Robustly Testable Array Multipliers under Realistic Sequential Cell Fault Model. VTS Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
1998	—	`conf`	SRAM-Based FPGA's: Testing the Interconnect/Logic Interface. Asian Test Symposium Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1998	B	`conf`	SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules. FPL Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1998	A	`conf`	SRAM-based FPGA's: testing the LUT/RAM modules. ITC Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1998	A	`conf`	Synthesis of BIST hardware for performance testing of MCM interconnections. ICCAD Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian
1998	A*	`conf`	System-Chip Test Strategies (Tutorial). DAC Yervant Zorian
1998	A	`conf`	Testing embedded-core based system chips. ITC Yervant Zorian, Erik Jan Marinissen, Sujit Dey
1998	J	`jnl`	Testing the Interconnect of RAM-Based FPGAs. IEEE Des. Test Comput. Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1997	A	`conf`	An Effective BIST Scheme for Arithmetic Logic Units. ITC Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian, Mihalis Psarakis
1997	J	`jnl`	An Effective Multi-Chip BIST Scheme. J. Electron. Test. Yervant Zorian, Hakim Bederr
1997	J	`jnl`	Design and Test of Core-Based Systems on Chips. IEEE Des. Test Comput. Yervant Zorian, Rajesh K. Gupta
1997	—	`conf`	Fault-secure shifter design: results and implementations. ED&TC Ricardo de Oliveira Duarte, Michael Nicolaidis, Hakim Bederr, Yervant Zorian
1997	J	`jnl`	Fundamentals of MCM Testing and Design-for-Testability. J. Electron. Test. Yervant Zorian
1997	J	`jnl`	Guest Editorial. J. Electron. Test. Yervant Zorian
1997	J	`jnl`	Introducing Core-Based System Design. IEEE Des. Test Comput. Rajesh K. Gupta, Yervant Zorian
1997	—	`conf`	On the generation of pseudo-deterministic two-patterns test sequence with LFSRs. ED&TC Christian Dufaza, Yervant Zorian
1997	Misc	`conf`	Power Dissipation During Testing: Should We Worry About it? VTS Vishwani D. Agrawal, Robert C. Aitken, J. Braden, Joan Figueras, S. Kumar, Hans-Joachim Wunderlich, Yervant Zorian
1997	Misc	`conf`	Systems On Silicon: Design and Test Challenges. VTS J. Borel, M. Cecchini, C. Malipeddi, Janusz Rajski, Yervant Zorian
1997	—	`conf`	Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA. Asian Test Symposium Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1997	A	`conf`	Test Requirements for Embedded Core-Based Systems and IEEE P1500. ITC Yervant Zorian
1997	Misc	`conf`	Test of RAM-based FPGA: methodology and application to the interconnect. VTS Michel Renovell, Joan Figueras, Yervant Zorian
1996	A	`conf`	An Effective BIST Scheme for Datapaths. ITC Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
1996	J	`jnl`	Conference Reports. IEEE Des. Test Comput. Gil Philips, Yervant Zorian, Charles W. Rosenthal, Bozena Kaminska
1996	—	`conf`	Designing Self-Testable Multi-Chip Modules. ED&TC Yervant Zorian, Hakim Bederr
1996	J	`jnl`	EIC Message. IEEE Des. Test Comput. Kenneth D. Wagner, Yervant Zorian
1996	J	`jnl`	Guest Editors' Introduction: East Meets West. IEEE Des. Test Comput. Yervant Zorian, Jan Hlavicka
1996	A	`conf`	Optimal Multiple Chain Relay Testing Scheme for MCMs on Large Area Substrates. ITC Koppolu Sasidhar, Abhijit Chatterjee, Yervant Zorian
1996	J	`jnl`	Panel Summaries. IEEE Des. Test Comput. Yervant Zorian, Tom Anderson, Yvon Savaria, Claude Thibeault, André Ivanov
1996	J	`jnl`	Programmable BIST Space Compactors. IEEE Trans. Computers André Ivanov, Barry K. Tsuji, Yervant Zorian
1996	—	`conf`	Relay Propagation Scheme for Testing of MCMs on Large Area Substrates. ED&TC Koppolu Sasidhar, Abhijit Chatterjee, Yervant Zorian
1995	A	`conf`	An Approach for Designing Total-Dose Tolerant MCMs Based on Current Monitoring. ITC Fabian Vargas, Michael Nicolaidis, Yervant Zorian
1995	A	`conf`	An Effective BIST Scheme for Booth Multipliers. ITC Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
1995	—	`conf`	An effective BIST scheme for carry-save and carry-propagate array multipliers. Asian Test Symposium Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
1995	—	`conf`	Area versus detection latency trade-offs in self-checking memory design. ED&TC O. Kebichi, Yervant Zorian, Michael Nicolaidis
1995	J	`jnl`	Conference Reports. IEEE Des. Test Comput. Sreejit Chakravarty, Ramalingam Sridhar, Shambhu J. Upadhyaya, Yervant Zorian, Gil Philips, Bozena Kaminska, Bernard Courtois
1995	—	`conf`	Functional test for shifting-type FIFOs. ED&TC Ad J. van de Goor, Ivo Schanstra, Yervant Zorian
1995	J	`jnl`	Integration of partial scan and built-in self-test. J. Electron. Test. Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik
1995	—	`conf`	Multi-chip module technology. ICNN Yervant Zorian
1994	A	`conf`	An Effective BIST Scheme for Ring-Address Type FIFOs. ITC Yervant Zorian, Ad J. van de Goor, Ivo Schanstra
1994	A	`conf`	Do You Practice Safe Tests? What We Found Out About Your Habits. ITC Cecil A. Dean, Yervant Zorian
1994	J	`jnl`	Effective march algorithms for testing single-order addressed memories. J. Electron. Test. Ad J. van de Goor, Yervant Zorian
1994	Misc	`conf`	Fault models and tests for Ring Address Type FIFOs. VTS Ad J. van de Goor, Ivo Schanstra, Yervant Zorian
1994	—	`conf`	Functional Tests for Ring-Address SRAM-type FIFOs. EDAC-ETC-EUROASIC Ad J. van de Goor, Yervant Zorian, Ivo Schanstra
1993	A	`conf`	A Method for Delay Fault Self-Testing of Macrocells. ITC Harold N. Scholz, Duane R. Aadsen, Yervant Zorian
1993	Misc	`conf`	A distributed BIST control scheme for complex VLSI devices. VTS Yervant Zorian
1993	A	`conf`	PSBIST: A Partial-Scan Based Built-In Self-Test Scheme. ITC Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik
1993	—	`conf`	Programmable Space Compaction for BIST. FTCS Yervant Zorian, André Ivanov
1992	C	`conf`	A Universal Testability Strategy for Multi-Chip Modules Based on BIST and Boundary-Scan. ICCD Yervant Zorian
1992	J	`jnl`	An Effective BIST Scheme for ROM's. IEEE Trans. Computers Yervant Zorian, André Ivanov
1992	J	`jnl`	Count-based BIST compaction schemes and aliasing probability computation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. André Ivanov, Yervant Zorian
1990	A	`conf`	Computing the Error Escape Probability in Count-Based Compaction Schemes. ICCAD André Ivanov, Yervant Zorian
1990	A	`conf`	EEODM: An effective BIST scheme for ROMs. ITC Yervant Zorian, André Ivanov
1990	J	`jnl`	Optimizing error masking in BIST by output data modification. J. Electron. Test. Yervant Zorian, Vinod K. Agarwal
1989	C	`conf`	Designing fault-tolerant, testable, VLSI processors using the IEEE P1149.1 boundary-scan architecture. ICCD Yervant Zorian, Najmi Jarwala
1984	A	`conf`	Higher Certainty of Error Coverage by Output Data Modification. ITC Yervant Zorian, Vinod K. Agarwal