Yeong-Jar Chang

19 papers A 4C 1Misc 1Journal 6Unranked 7
YearRankTypeTitle / Venue / Authors
2025 J jnl
Mixed-Signal Quantum Circuit Design for Option Pricing Using Design Compiler.
CoRR
Yu-Ting Kao, Yeong-Jar Chang, Ying-Wei Tseng
2025 — conf
Quantum-Chiplet: A VLSI-Like Methodology for Hierarchical Quantum Design and Verification.
ISVLSI
Hao-Yu Lu, Yu-Ting Kao, Yeong-Jar Chang, Jason Gemsun Young, Darsen D. Lu
2025 J jnl
Quantum-Train: rethinking hybrid quantum-classical machine learning in the model compression perspective.
Quantum Mach. Intell.
Chen-Yu Liu, En-Jui Kuo, Chu-Hsuan Abraham Lin, Jason Gemsun Young, Yeong-Jar Chang, Min-Hsiu Hsieh, Hsi-Sheng Goan
2024 Misc conf
Training Classical Neural Networks by Quantum Machine Learning.
QCE
Chen-Yu Liu, En-Jui Kuo, Chu-Hsuan Abraham Lin, Sean Chen, Jason Gemsun Young, Yeong-Jar Chang, Min-Hsiu Hsieh
2021 J jnl
Thermal-Aware Fixed-Outline Floorplanning Using Analytical Models With Thermal-Force Modulation.
IEEE Trans. Very Large Scale Integr. Syst.
Jai-Ming Lin, Tai-Ting Chen, Hao-Yuan Hsieh, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu
2021 J jnl
Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC.
IEEE Trans. Very Large Scale Integr. Syst.
Jai-Ming Lin, Wei-Yi Chang, Hao-Yuan Hsieh, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu
2019 — conf
Intelligent Policy Selection for GPU Warp Scheduler.
AICAS
Lih-Yih Chiou, Tsung-Han Yang, Jian-Tang Syu, Che-Pin Chang, Yeong-Jar Chang
2018 A conf
A fast thermal-aware fixed-outline floorplanning methodology based on analytical models.
ICCAD
Jai-Ming Lin, Tai-Ting Chen, Yen-Fu Chang, Wei-Yi Chang, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu
2018 — conf
Fast Steady-State Thermal Analysis.
ISOCC
Lih-Yih Chiou, Chun-Hao Chang, Liang-Ying Lu, Wei-Hsuan Yang, Yeong-Jar Chang, Juin-Ming Lu
2010 J jnl
Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang, Yeong-Jar Chang
2009 C conf
On the Design of Power-rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-voltage CMOS Process.
ISCAS
Ming-Dou Ker, Po-Yen Chiu, Fu-Yi Tsai, Yeong-Jar Chang
2009 A conf
Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs.
ICCAD
Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang, Yeong-Jar Chang
2008 A conf
A Low-Cost Programmable Memory BIST Design for Multiple Memory Instances.
ITC
Chung-Fu Lin, Chia-Fu Huang, De-Chung Lu, Chih-Chiang Hsu, Wen-Tsung Chiu, Yu-Wei Chen, Yeong-Jar Chang
2005 — conf
Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle.
Asian Test Symposium
Ming Shae Wu, Chung-Len Lee, Yeong-Jar Chang, Wen Ching Wu
2004 — conf
A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories.
MTDT
Li-Ming Denq, Rei-Fu Huang, Cheng-Wen Wu, Yeong-Jar Chang, Wen Ching Wu
2004 — conf
Fail Pattern Identification for Memory Built-In Self-Repair.
Asian Test Symposium
Rei-Fu Huang, Chin-Lung Su, Cheng-Wen Wu, Shen-Tien Lin, Kun-Lun Luo, Yeong-Jar Chang
2004 A conf
MRAM Defect Analysis and Fault Modeli.
ITC
Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen Ching Wu
2000 J jnl
A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier.
J. Inf. Sci. Eng.
Yeong-Jar Chang, Chung-Len Lee, Jwu E. Chen, Chauchin Su
1994 — conf
Synthesis of Multi-Variable MVL Funtions Using Hybrid Mode CMOS Logic.
ISMVL
Yeong-Jar Chang, Chung-Len Lee